Towards complete pulpv3 coverage #3
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Specify --ust-trace FILE to record execution trace in cvs format to FILE.
This prevents an error message ("Failed to open ust trace file:") when
--ust-trace is not specified.
The mempool version of Spike is a lot more up-do-date and implements many new instructions. Overwrite all with contents from toolchain/riscv-isa-sim pulp-platform/mempool@32eab8e
The instructions are not yet integrated into the build-procedure.
It would also be possible to just add all the remaining instructions to the existing variable but splitting it better represents how the extension is organized everywhere else.
This implementation was only tested against the very simple example in the CV32E40P docs, so it might not always work properly. 1. Implement a hardware-loop unit in processor_t, add the CSRs to state_t (incl set_csr and get_csr handling) 2. Add the hw-loop unit to the cycle-execution loop in execute.cc 3. Add instructions to write to hwloop CSRs Currently not all constraints are checked yet (illegal instrs in body).
The guards are not consistently used across all relevant code. This might be a project for the future, a better guard condition is also needed (directly conditioned on the presence of the extension, not on an instruction in it).
Now you can pass expressions without violating order-of-operation.
- Add disassembly format - Add signed/zero-extend and extract macro to easily access a range of bits in a register - Implement all instructions (if possible using gcc builtins) - Add set properly to make This implementation is tested against automatically generated tests.
I removed it everywhere else but didn't catch this one.
I can't run the test (can't compile it since xpulpbitrev is not an extension in gcc), therefore this implementation is experimental. I did however compile the exact same code separately and run it against the examples from the docs, so if it fails it is likely in an edge-case.
- Add disassembly format - Implement all instructions - Add it to make This implementation is tested against generated tests.
- Add disassembly format - Implement all instructions - Add it to make This implementation is tested against generated tests.
- Add disassembly format - Implement all instructions - Add it to make This implementation is tested against generated tests.
- Added union for easier SIMD handling
- Add disassembly format
- Implement remaining instructions
(all compare instrs, add_div{2,4,8} and sub_div{2,4,8}
- Add remaining instrs to make
This implementation is tested against generated tests.
- Add disassembly format - Implement all instructions - Add instructions to make This implementation is tested against generated tests.
For gcc buitins are used, until now only they were tested. The alternative implementations have now been fixed and tested as well.
Mention xpulp isa and other useful repos. Add baremetal example and link to more.
This was referenced Jun 21, 2023
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Adds functional implementation of almost all instructions in pulpv3 (elw is missing).
This was done as a SoCDAML miniproject in summer 2022.
The entire project consists of changes to:
pulp-platform/riscv-opcodes#8
pulp-platform/riscv-isa-sim
pulp-platform/riscv-tests#5
All are necessary for the goal of having definitions (riscv-opcodes), a reference (riscv-isa-sim) and tests (risv-tests) for the pulpv3 instruction set.
Attached is a slide from the presentation of the project, it shows which instructions were added.
presentation.pdf