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Update riscv-elf.adoc
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Co-authored-by: Jessica Clarke <[email protected]>
Signed-off-by: Rui Ueyama <[email protected]>
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rui314 and jrtc27 authored Sep 28, 2023
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Expand Up @@ -1580,7 +1580,7 @@ NOTE: Tag_RISCV_x3_reg_usage is treated as 0 if it is not present.
Description:: This relaxation can relax a GOT indirection into load
immediate or PC-relative addressing. This relaxation is intended to
optimize the `la`/`lga` assembly pseudo-instruction, which loads a
symbol's address from a GOT entry with an `auipc` + `ld` instruction
symbol's address from a GOT entry with an `auipc` + `l[w|d]` instruction
pair.

Condition::
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