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Updates to address issue #36 #37

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merged 8 commits into from
Nov 27, 2023

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@@ -414,20 +442,22 @@ the hardware unit.
{bits: 1, name: 'c'},

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I was expecting to see a set of bits associated with the error event to provide details about the specifics of the event and subsume bits like c and scrub.

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A set of bits in the status_i register are designated for future standard use and may be defined by future standard extensions for additional qualifiers.

@@ -446,8 +446,7 @@ the hardware unit.
{bits: 4, name: 'ait'},
{bits: 1, name: 'siv'},
{bits: 1, name: 'tsv'},
{bits: 2, name: 'WPRI'},
{bits: 1, name: 'scrub'},
{bits: 3, name: 'WPRI'},

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Ved, this bit has value in enabling the RAS agent to quickly determine if and what action it should take. There should be more than one bit. My desire was that it be subsumed by a set of qualifier or other readily available bits of information to support that. Since those bits are NOT part of this revision as I requested, I am concerned about removing it now.

I am fully supportive of moving and consolidating such bits to enable a later incorporation of them into a more capable qualifier rather that having them being spread across different parts of the status register, but there is still value here.

@ved-rivos ved-rivos merged commit fe22c7c into riscv-non-isa:main Nov 27, 2023
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2 participants