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Simple and obvious changes in Chapter 2 (from PR#19)
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[[header]]
:description: RISC-V N-Trace (Nexus-based Trace)
:company: RISC-V.org
:revdate: Sep 11, 2023
:revnumber: 1.0.0_rc9
:revremark: Frozen state (before Architecture Committee review)
:revdate: Nov 28, 2023
:revnumber: 1.0.0_rc10
:revremark: Stable state (before Architecture Committee review)
:url-riscv: http://riscv.org
:doctype: book
:preface-title: Preamble
Expand Down Expand Up @@ -40,7 +40,7 @@ RISC-V N-Trace Task Group

// Preamble
[WARNING]
.This document is in the link:http://riscv.org/spec-state[Frozen state]
.This document is in the link:http://riscv.org/spec-state[Stable state]
====
Change is extremely unlikely.
====
Expand All @@ -50,8 +50,9 @@ Change is extremely unlikely.

PDF generated on: {localdatetime}

=== Version 1.0.0_rc9
* 2023-09-11
=== Version 1.0.0_rc10
* 2023-11-28
** Made obvious changes from PR#19
** The pre-public review version (older history removed)

[Preface]
Expand All @@ -70,7 +71,7 @@ Please cite as: “RISC-V N-Trace (Nexus-based Trace) Specification", RISC-V In
Key contributors to RISC-V N-Trace (Nexus-based Trace) specification in alphabetical order: +

Bruce Ableidinger (SiFive) => Initial SiFive donation, reviews +
Robert Chyla (IAR, SiFive) => Most topics, editing, publishing +
Robert Chyla (IAR, SiFive, Individual) => Most topics, editing, publishing +
Ernie Edgar (SiFive) => Initial SiFive donation, reviews +
Jay Gamoneda (NXP) => Reviews +
Markus Goehrle (Lauterbach) => Reviews, updates +
Expand Down Expand Up @@ -203,19 +204,19 @@ N-Trace is using the same ingress port as specified in <<E-Trace_Specification,E
* As this specification does not define the data trace yet, sub-chapters *4.3 Data Trace Interface requirements* and *4.4 Data Trace Interface* are not applicable.
* It is an ambition to extract single, shared *RISC-V Trace Ingress Port* specifications (combining this chapter with relevant E-Trace chapter).

Table below provides a detailed mapping of encodings of instructions into *itype* signal - it should be used during development of ingress port logic inside of a hart. Please be aware that not only instructions, but also arguments matter (for example jalr rd,rs1 may generate 5 different, distinct *itype* values).
Table below provides a detailed mapping of of causes for terminating an instruction block to the corresponding *itype* encoding - it could be used during development of ingress port logic inside of a hart. Please be aware that not only instructions, but also arguments matter (for example jalr rd,rs1 may generate 5 different, distinct *itype* values).

[#Generating itype for different instructions]
.Generating itype for different instructions
[cols="25%,40%,35%",options="header",]
|======================================================================================================
|Instruction Retired|Condition/Notes|itype Value
|Interrupted instruction|Any instruction|2 = Interrupt
|Exception in instruction|Any instruction|1 = Exception
|Instruction|Condition/Notes|itype Value
|Interrupted instruction|An interrupt trap occurred following the final retired instruction in the block|2 = Interrupt
|Exception in instruction|An exception trap that occurred following the final retired instruction in the block|1 = Exception
|Conditional branch|Non-taken |4 = Non-taken branch
||Taken |5 = Taken branch
|ebreak, ecall, c.ebreak|ecall is reported after retirement |1 = Exception
|mret, sret, uret| |3 = Exception or interrupt return
|mret, sret| |3 = Exception or interrupt return
|cm.jt |Defined by Zcmt extension |0 = No special type
|non-jump| |0 = No special type
3+|*Values of itype (4-bit) needed for <<Implicit Return Optimization,Implicit Return Optimization>>*
Expand All @@ -233,7 +234,7 @@ Table below provides a detailed mapping of encodings of instructions into *itype
| |rs1 != `link` |14 = Other uninferable jump
|c.j |No registers, only offset |15 = Other inferable jump
|cm.jalt |Defined by Zcmt extension |9 = Inferable call
|cm.popret* |Defined by zcmp extension |13 = Return
|cm.popret* |Defined by Zcmp extension |13 = Return
3+|*Values of itype (3-bit) without <<Implicit Return Optimization,Implicit Return Optimization>>*
|jal rd | |0 = No special type
|jalr | |6 = Uninferable jump
Expand All @@ -260,13 +261,13 @@ Table below defines how N-Trace encoder should handle different 3-bit *itype* va
|0|None below|Only update <<field_I-CNT,I-CNT>> field.
|1|Exception|Update <<field_I-CNT,I-CNT>> field. +
Emit Indirect Branch message with <<field_B-TYPE,B-TYPE>>=2 or 1. +
*IMPORTANT:* An address emitted is known at the next ingress port cycle.
*IMPORTANT:* An address emitted is known at the next valid ingress port cycle.
|2|Interrupt|Update <<field_I-CNT,I-CNT>> field. +
Emit Indirect Branch message with <<field_B-TYPE,B-TYPE>>=3 or 1. +
*IMPORTANT:* An address emitted is known at the next ingress port cycle.
*IMPORTANT:* An address emitted is known at the next valid ingress port cycle.
|3|Exception or interrupt return|Update <<field_I-CNT,I-CNT>> field. +
Emit Indirect Branch message with <<field_B-TYPE,B-TYPE>>=0. +
*IMPORTANT:* An address emitted is known at the next ingress port cycle.
*IMPORTANT:* An address emitted is known at the next valid ingress port cycle.
|4|Non-taken branch|*For BTM mode:* +
Only update <<field_I-CNT,I-CNT>> field.

Expand All @@ -280,37 +281,37 @@ Emit Indirect Branch message with <<field_B-TYPE,B-TYPE>>=0. +
*For HTM mode:* +
Update <<field_I-CNT,I-CNT>> field. +
Add 1 as LSB bit to HIST field. See <<HIST Field Overflows, HIST Field Overflows>> for handling of overflow.
|6|Un-inferable jump|Update <<field_I-CNT,I-CNT>> field. +
|6|Uninferable jump|Update <<field_I-CNT,I-CNT>> field. +
Emit Indirect Branch message with <<field_B-TYPE,B-TYPE>>=0. +
*IMPORTANT:* An address emitted is known at the next ingress port cycle.
*IMPORTANT:* An address emitted is known at the next valid ingress port cycle.
|7|Reserved|-
|======================================================================================================

When ingress port is implemented as 4-bit, the general un-inferable jump *itype=6* should not be generated and one of the following values should be generated instead. Encode must handle call stack as described in the <<Implicit Return Optimization,Implicit Return Optimization>> chapter.
When ingress port is implemented as 4-bit, the general uninferable jump *itype=6* should not be generated and one of the following values should be generated instead. Encode must handle call stack as described in the <<Implicit Return Optimization,Implicit Return Optimization>> chapter.

[#Handling of 4-bit itype values]
.Handling of 4-bit itype values
[cols="7%,23%,58%,12%",options="header",]
|======================================================================================================
|8|Un-inferable call|Update <<field_I-CNT,I-CNT>> field. Emit Indirect Branch message with <<field_B-TYPE,B-TYPE>>=0|Push
|8|Uninferable call|Update <<field_I-CNT,I-CNT>> field. Emit Indirect Branch message with <<field_B-TYPE,B-TYPE>>=0|Push
|9|Inferrable call|Only update <<field_I-CNT,I-CNT>> field.|Push
|10|Un-inferable tail-call|*NOT POSSIBLE* (see <<Custom Instructions,Custom Instructions>>)|-
|10|Uninferable tail-call|*NOT POSSIBLE* (see <<Custom Instructions,Custom Instructions>>)|-
|11|Inferrable tail-call|*NOT POSSIBLE* (see <<Custom Instructions,Custom Instructions>>)|-
|12|Co-routine swap|Update <<field_I-CNT,I-CNT>> field. +
If Pop returns the same address as PC at next ingress port cycle, emit Indirect Branch message with <<field_B-TYPE,B-TYPE>>=0.|Pop,Push
If Pop returns the same address as PC at next valid ingress port cycle, emit Indirect Branch message with <<field_B-TYPE,B-TYPE>>=0.|Pop,Push
|13|Return|Update <<field_I-CNT,I-CNT>> field. +
If Pop returns the same address as PC at next ingress port cycle, emit Indirect Branch message with <<field_B-TYPE,B-TYPE>>=0.
If Pop returns the same address as PC at next valid ingress port cycle, emit Indirect Branch message with <<field_B-TYPE,B-TYPE>>=0.
|Pop
|14|Other un-inferable jump|Update <<field_I-CNT,I-CNT>> field. +
|14|Other uninferable jump|Update <<field_I-CNT,I-CNT>> field. +
Emit Indirect Branch message with <<field_B-TYPE,B-TYPE>>=0.|-
|15|Other inferable jump|Only update <<field_I-CNT,I-CNT>> field.|-
|======================================================================================================

As almost every ingress port cycle is updating I-CNT it may overflow. See <<I-CNT Field Overflows, I-CNT Field Overflows>> for more details.
IMPORTANT: N-Trace encoder does not require *cause* and *tval* ingress port signals (valid for exceptions and interrupts only) as these are not reported in N-Trace messages. N-Trace is only providing the address of an exception/interrupt handler.

NOTE: If optional <<trTeInstEnAllJumps,trTeInstEnAllJumps>> bit is set, trace ingress port must report *itype*=5 (Taken branch) for all direct unconditional jumps (which are normally reported as *itype* = 0). It is also possible (for implementation of both ingress port inside of a core and N-Trace encoder) to use reserved *itype*=7 for that purpose - in such a case trace encoder should handle *itype*=7 as value 0 or 5.
NOTE: As almost every ingress port cycle is updating I-CNT it may overflow. See <<I-CNT Field Overflows, I-CNT Field Overflows>> for more details.

IMPORTANT: N-Trace encoder does not require *cause* and *tvar* ingress port signals (valid for exceptions and interrupts only) as these are not reported in N-Trace messages. N-Trace is only providing the address of an exception/interrupt handler.
NOTE: If optional <<trTeInstEnAllJumps,trTeInstEnAllJumps>> bit is set, trace ingress port must report *itype*=5 (Taken branch) for all direct unconditional jumps (which are normally reported as *itype* = 0 or 15).

== N-Trace Transmission Protocol

Expand All @@ -323,6 +324,8 @@ N-Trace specification defines 6-bit *MDO* and 2-bit *MSEO* so both fit in a sing

N-Trace messages transmission protocol is a strict subset of Nexus trace messaging protocol.

[N-Trace subset]
.N-Trace subset
[cols="33%,22%,45%",options="header",]
|====
|Protocol Feature|Defined in Nexus IEEE 5001|N-Trace (strict subset of Nexus)
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