isa zve64x with doule & single floating-point extension

[alextxia13]

According to riscv-v-spec, I think we can define vector isa to zve64x with extension F & D to support Floating-point instruction but not vector floating-point instruction. Is the isa legal to support DF_zve64x?
The vfmv, vfncvt and vfwcvt instruction, in spike now, use extension 'D' & 'F' to check illegal. However, if the isa above supported, these instruction should be illegal when isa both has extension 'D' or 'F' with Zve64x.
Please help to take a look, thanks!

[aswaterman]

Those instructions are reserved for Zve64x. So, implementing them in Spike is not technically invalid, but it is an error of intent. It is low priority, but they probably should be changed to raise an illegal-instruction exception in this case.