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Pull requests: riscv-software-src/riscv-isa-sim

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Pull requests list

Add DCSR.MPRVEN support
#1882 opened Dec 20, 2024 by fk-sc Loading…
Fix read value of CSR mip.
#1869 opened Dec 9, 2024 by NewPaulWalker Loading…
Add Shlcofideleg support
#1847 opened Oct 31, 2024 by demin-han Loading…
Add instruction limit
#1828 opened Oct 4, 2024 by Timmmm Loading…
Fix dtc_output read when interrupted by EINTR
#1801 opened Sep 10, 2024 by MarcoBonino Loading…
README.md: update "Debugging With Gdb"
#1800 opened Sep 9, 2024 by hirooih Loading…
Check tcontrol.mte in trigger_t::allow_action()
#1777 opened Aug 16, 2024 by rtwfroody Loading…
Vector crypto additional
#1748 opened Jul 25, 2024 by nibrunieAtSi5 Draft
hvip: Correct logging value of mip on writing hvip
#1741 opened Jul 23, 2024 by YenHaoChen Loading…
Update mcontrol6 to support version 1.0
#1667 opened May 14, 2024 by rtwfroody Loading…
AIA: Implement Smaia/Ssaia extension
#1635 opened Mar 29, 2024 by YenHaoChen Loading…
don't read CSR in csrrw(i) with rd=0
#1628 opened Mar 19, 2024 by ShengMingTangAndes Loading…
UB in negate in mulh/mulhsu
#1546 opened Dec 21, 2023 by nibrunieAtSi5 Draft
Add Ssdtso support
#1501 opened Nov 13, 2023 by cmuellner Loading…
[vector-crypto] Fixing Zvkb/Zvbb distinction
#1474 opened Sep 29, 2023 by nibrunieAtSi5 Loading…
fix: mcontrol/mcontrol6 on fetch
#1459 opened Sep 13, 2023 by YenHaoChen Loading…
ProTip! What’s not been updated in a month: updated:<2024-11-24.