Disable NEON intrinsics on big-endian ARM #1485
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@Amanieu: no appropriate reviewer found, use r? to override |
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@rust-lang/libs-api @rust-lang/libs This is a breaking change, but a necessary one in my opinion until the intrinsics are fixed. They currently silently produce the wrong results, which has led to a bug in hashbrown on big-endian ARM: rust-lang/rust#116880 |
These are currently broken because the order of elements inside vectors is reversed on big-endian systems: the ARM ABI requires that element 0 is located at the highest address of the vector type. However LLVM intrinsics expect element 0 to be located at the lowest address. See https://llvm.org/docs/BigEndianNEON.html and `arm_neon.h` in Clang for more details. Although this is a breaking change, this is acceptable for 2 reasons: - big endian ARM targets are only tier 3. - it is preferable to stop existing code from compiling than to let it run and produce incorrect results.
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@rustbot ping arm |
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Fixing this is not likely to be quick or easy, so I agree that disabling them for BE targets is probably the best approach for now. |
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These are currently broken because the order of elements inside vectors is reversed on big-endian systems: the ARM ABI requires that element 0 is located at the highest address of the vector type. However LLVM intrinsics expect element 0 to be located at the lowest address.
See https://llvm.org/docs/BigEndianNEON.html and
arm_neon.hin Clang for more details.This is tracked in #1484.
Although this is a breaking change, this is acceptable for 2 reasons: