Padring generator upgrade

lambdalib/iolib/README.md

@@ -24,7 +24,7 @@
 ## PARAMETERS
 
 ### CFGW
-The `CFGW` parameter defines the width of the configuration bus of the io cell. IO cells generally include a set of configuration inputs for things like drive strength and operating modes. Setting `CFGW` to a large value (eg. 16/32) should have zero impact on the design as the extra bus bits get optimized away during implementation.
+The `CFGW` parameter defines the width of the configuration bus of the io cell. IO cells generally include a set of configuration inputs for things like drive strength and operating modes. Setting `CFGW` to a large value (eg. 16/32) should have zero impact on the design as the extra bus bits get optimized away during implementation. The connection between the generic `CFG` bus and the technology specific IO cell is done within the techology specific cell wrapper library.
 
 For la_bidir, the first 8 bits of the configuration bus are reserved for the functionality shown in the table below.
 

lambdalib/padring/README.md

@@ -1,4 +1,4 @@
-# PADRING GENERATOR
+q# PADRING GENERATOR
 
 ## Introduction
 
@@ -18,8 +18,8 @@ Specifies the total number of power sections within one side of the padring. The
 ### {NO,EA,WE,SO}CELLMAP
 Specifies the type of cells, pin connections, properties, and power connections of all cells in the padring with the exception of filler cells. The physical placement of the cells within the padring shall be done in the order dictated by `CELLMAP`. The CELLMAP is a vector of size NCELLS * 40, with the 40bit vector split into the following fields:
 
-  * PIN[7:0]     = CELLMAP[7:0]   = pin number connected to cell
-  * COMP[7:0]    = CELLMAP[15:8]  = pin number for complementary pad for differential cells
+  * PIN[7:0]     = CELLMAP[7:0]   = pin number connected to cell. Positive signal in case of differential pairs.
+  * COMP[7:0]    = CELLMAP[15:8]  = pin number of complementary (negative) pad to `PIN`. Used for differential IO cells.
   * TYPE[7:0]    = CELLMAP[23:16] = cell type (see ./la_padring.vh)
   * SECTION[7:0] = CELLMAP[31:24] = padring power section number connected to cell
   * PROP[7:0]    = CELLMAP[39:32] = property passed to technology specific iolib implementation
@@ -30,7 +30,7 @@ The header file [la_iopadring.vh](./rtl/la_iopadring.vh) enumerates the cells re
 Specifies the width of the configuration bus of the io cell. For a description of uses of `CFGW`, see [IOLIB](../../iolib/README.md).
 
 #### RINGW
-The `RINGW` parameter specifies the number of signals within the power bus that connects all of the io cells together within the padring.
+The `RINGW` parameter specifies the number of signals within the power bus that connects all of the io cells together within the padring. For a description of uses of `RINGW`, see [IOLIB](../../iolib/README.md).
 
 
 ## Using the Generator

lambdalib/padring/rtl/la_ioalias.v

@@ -0,0 +1,25 @@
+
+/**************************************************************************
+ * Function: IO Alias Utility Module
+ * Copyright: Lambda Project Authors. All rights Reserved.
+ * License:  MIT (see LICENSE file in Lambda repository)
+ *
+ * Docs:
+ *
+ * Signal renaming and concatenation of wires doesn't work for
+ * directly connected I/O ports. One solution is to hard code the
+ * connections in the design. Another option is to pass through the
+ * name translation module shown below.
+ *
+ * WARNING: The port list alias features is in the verilog standard,
+ * but not well supported by open source tools. Not recommended for
+ * portable designs.
+ *
+ *************************************************************************/
+
+module la_ioalias (.io1(a),
+                   .io2(a));
+
+   inout wire a;
+
+endmodule

lambdalib/padring/rtl/la_ioshort.v

@@ -0,0 +1,31 @@
+/**************************************************************************
+ * Function: Simulation Friendly IO Alias Module
+ * Copyright: Lambda Project Authors. All rights Reserved.
+ * License:  MIT (see LICENSE file in Lambda repository)
+ *
+ * Docs:
+ *
+ * Instantiates the la_ioalias inout alias module and adds a loop breaking
+ * logic for some tools that don's support tran, alias,and port aliasing.
+ *
+ * WARNING: The port list alias features is in the verilog standard,
+ * but not well supported by open source tools. Not recommended for
+ * portable designs.
+ *
+ *************************************************************************/
+module la_ioshort (inout a,
+                   inout b,
+                   input a2b
+                   );
+
+`ifdef VERILATOR
+   // Using direction to break the loop
+   assign a = ~a2b ? b : 1'bz;
+   assign b = a2b ? a : 1'bz;
+`else
+    // verilog_lint: waive-start module-port
+    la_pt la_ioalias (a,b);
+    // verilog_lint: waive-end module-port
+`endif
+
+endmodule