Merge pull request #56 from slaclab/pre-release

v3.1.2 release candidate

.travis.yml

@@ -0,0 +1,87 @@
+# This will run on Travis' 'new' container-based infrastructure
+sudo: true
+
+# Setup for Ubuntu Bionic (18.04)
+dist: bionic
+
+language:
+  - python
+
+python:
+  - 3.6
+
+# Environment variables
+env:
+  global:
+    - PACKAGE_DIR: $HOME/packages
+    - DOXYFILE: $TRAVIS_BUILD_DIR/Doxyfile
+    - MINICONDA_DIR: $PACKAGE_DIR/miniconda
+
+# Install dependencies
+addons:
+  apt:
+    packages:
+      - python3
+
+stages:
+    - name: deploy_dev
+      if: branch = pre-release AND tag IS blank AND NOT (type = pull_request)
+    - name: deploy_tag
+      if: tag IS present
+
+# Generate and deploy documentation
+jobs:
+  include:
+    - &deploy-conda-stage       # Conda for linux
+      stage: deploy_dev
+      name: "Deploy Conda"
+      env: CONDA_TOKEN=$CONDA_UPLOAD_TOKEN_DEV
+      before_install:
+        # Prepare folders
+        - mkdir -p $MINICONDA_DIR
+        # Bring all the tags
+        - git pull --unshallow
+        - git pull
+        # on OSX rogue needs an older version of the MacOS SDK
+        - if [[ "$TRAVIS_OS_NAME" == "osx" ]]; then
+            git clone https://github.com/phracker/MacOSX-SDKs;
+            sudo mv MacOSX-SDKs/MacOSX10.9.sdk /opt/;
+            export CONDA_BUILD_SYSROOT=/opt/MacOSX10.9.sdk;
+            export CONDA_BUILD=1;
+          fi
+
+      install:
+        # Install Anaconda for the right architecture (linux or osx)
+        - cd $MINICONDA_DIR
+        - if [[ "$TRAVIS_OS_NAME" == "osx" ]]; then
+            wget -O miniconda.sh https://repo.continuum.io/miniconda/Miniconda3-latest-MacOSX-x86_64.sh;
+          else
+            wget -O miniconda.sh https://repo.continuum.io/miniconda/Miniconda3-latest-Linux-x86_64.sh;
+          fi
+        - bash miniconda.sh -b -p $HOME/miniconda
+        - export PATH="$HOME/miniconda/bin:$PATH"
+        - hash -r
+        - conda config --set always_yes yes
+        - conda install conda-build anaconda-client conda-verify
+        - conda update -q conda conda-build
+
+      before_script:
+        # Go back to top directory
+        - cd $TRAVIS_BUILD_DIR
+
+      script:
+        # Build conda package
+        - travis_wait 60 conda build --debug conda-recipe --output-folder bld-dir -c tidair-tag -c conda-forge
+
+      after_success:
+        # Upload conda package
+        - anaconda -t $CONDA_TOKEN upload bld-dir/`echo $TRAVIS_OS_NAME`-64/*.tar.bz2
+
+    - <<: *deploy-conda-stage   # Conda for MacOS
+      os: osx
+      language: ruby  # osx does not support language=python
+
+    - <<: *deploy-conda-stage   # Conda for Linux
+      stage: deploy_tag
+      env: CONDA_TOKEN=$CONDA_UPLOAD_TOKEN_TAG
+

conda-recipe/README.md

@@ -0,0 +1,8 @@
+
+#### Building conda package
+
+````
+$ conda build --debug conda-recipe --output-folder bld-dir -c tidair-packages -c tidair-tag -c conda-forge
+$ conda activate
+$ anaconda upload bld-dir/linux-64/rogue-.....
+````

conda-recipe/build.sh

@@ -0,0 +1,4 @@
+#!/usr/bin/bash
+
+python setup.py install
+

conda-recipe/meta.yaml

@@ -0,0 +1,29 @@
+package: 
+  name: axi_pcie_core
+  version: {{ GIT_DESCRIBE_TAG }}
+
+source:
+   path: ..
+
+build:
+   number: {{ GIT_DESCRIBE_NUMBER|int }}
+
+requirements:
+   build:
+     - python
+     - rogue
+     - git
+     - gitpython
+     - numpy
+
+   run:
+     - python
+     - rogue
+     - numpy
+
+about:
+   home: https://github.com/slaclab/axi-pcie-core
+   license: SLAC Open License
+   license_file: LICENSE.txt
+   summary: AXI PCIE Core Library
+

hardware/SlacPgpCardG3/rtl/AxiPcieCrossbar.vhd

@@ -32,10 +32,10 @@ entity AxiPcieCrossbar is
       axiClk           : in  sl;
       axiRst           : in  sl;
       -- Slaves
-      sAxiWriteMasters : in  AxiWriteMasterArray(DMA_SIZE_G downto 0);
-      sAxiWriteSlaves  : out AxiWriteSlaveArray(DMA_SIZE_G downto 0);
-      sAxiReadMasters  : in  AxiReadMasterArray(DMA_SIZE_G downto 0);
-      sAxiReadSlaves   : out AxiReadSlaveArray(DMA_SIZE_G downto 0);
+      sAxiWriteMasters : in  AxiWriteMasterArray(DMA_SIZE_G+1 downto 0);
+      sAxiWriteSlaves  : out AxiWriteSlaveArray(DMA_SIZE_G+1 downto 0);
+      sAxiReadMasters  : in  AxiReadMasterArray(DMA_SIZE_G+1 downto 0);
+      sAxiReadSlaves   : out AxiReadSlaveArray(DMA_SIZE_G+1 downto 0);
       -- Master
       mAxiWriteMaster  : out AxiWriteMasterType;
       mAxiWriteSlave   : in  AxiWriteSlaveType;
@@ -59,6 +59,16 @@ begin
       sAxiReadSlaves(i)  <= axiReadSlaves(i);
    end generate;
 
+   -- --------------------------------------------------------------
+   -- -- No resizing required for User General Purpose AXI Interface
+   -- --------------------------------------------------------------
+   -- axiWriteMasters(DMA_SIZE_G+1) <= sAxiWriteMasters(DMA_SIZE_G+1);
+   -- sAxiWriteSlaves(DMA_SIZE_G+1) <= axiWriteSlaves(DMA_SIZE_G+1);
+   -- axiReadMasters(DMA_SIZE_G+1)  <= sAxiReadMasters(DMA_SIZE_G+1);
+   -- sAxiReadSlaves(DMA_SIZE_G+1)  <= axiReadSlaves(DMA_SIZE_G+1);
+   sAxiWriteSlaves(DMA_SIZE_G+1) <= AXI_WRITE_SLAVE_FORCE_C;
+   sAxiReadSlaves(DMA_SIZE_G+1)  <= AXI_READ_SLAVE_FORCE_C;
+
    -------------------
    -- AXI XBAR IP Core
    -------------------

hardware/XilinxAc701/rtl/AxiPcieCrossbar.vhd

@@ -32,10 +32,10 @@ entity AxiPcieCrossbar is
       axiClk           : in  sl;
       axiRst           : in  sl;
       -- Slaves
-      sAxiWriteMasters : in  AxiWriteMasterArray(DMA_SIZE_G downto 0);
-      sAxiWriteSlaves  : out AxiWriteSlaveArray(DMA_SIZE_G downto 0);
-      sAxiReadMasters  : in  AxiReadMasterArray(DMA_SIZE_G downto 0);
-      sAxiReadSlaves   : out AxiReadSlaveArray(DMA_SIZE_G downto 0);
+      sAxiWriteMasters : in  AxiWriteMasterArray(DMA_SIZE_G+1 downto 0);
+      sAxiWriteSlaves  : out AxiWriteSlaveArray(DMA_SIZE_G+1 downto 0);
+      sAxiReadMasters  : in  AxiReadMasterArray(DMA_SIZE_G+1 downto 0);
+      sAxiReadSlaves   : out AxiReadSlaveArray(DMA_SIZE_G+1 downto 0);
       -- Master
       mAxiWriteMaster  : out AxiWriteMasterType;
       mAxiWriteSlave   : in  AxiWriteSlaveType;
@@ -59,6 +59,16 @@ begin
       sAxiReadSlaves(i)  <= axiReadSlaves(i);
    end generate;
 
+   -- --------------------------------------------------------------
+   -- -- No resizing required for User General Purpose AXI Interface
+   -- --------------------------------------------------------------
+   -- axiWriteMasters(DMA_SIZE_G+1) <= sAxiWriteMasters(DMA_SIZE_G+1);
+   -- sAxiWriteSlaves(DMA_SIZE_G+1) <= axiWriteSlaves(DMA_SIZE_G+1);
+   -- axiReadMasters(DMA_SIZE_G+1)  <= sAxiReadMasters(DMA_SIZE_G+1);
+   -- sAxiReadSlaves(DMA_SIZE_G+1)  <= axiReadSlaves(DMA_SIZE_G+1);
+   sAxiWriteSlaves(DMA_SIZE_G+1) <= AXI_WRITE_SLAVE_FORCE_C;
+   sAxiReadSlaves(DMA_SIZE_G+1)  <= AXI_READ_SLAVE_FORCE_C;
+
    -------------------
    -- AXI XBAR IP Core
    -------------------

hardware/XilinxKc705/rtl/AxiPcieCrossbar.vhd

@@ -32,10 +32,10 @@ entity AxiPcieCrossbar is
       axiClk           : in  sl;
       axiRst           : in  sl;
       -- Slaves
-      sAxiWriteMasters : in  AxiWriteMasterArray(DMA_SIZE_G downto 0);
-      sAxiWriteSlaves  : out AxiWriteSlaveArray(DMA_SIZE_G downto 0);
-      sAxiReadMasters  : in  AxiReadMasterArray(DMA_SIZE_G downto 0);
-      sAxiReadSlaves   : out AxiReadSlaveArray(DMA_SIZE_G downto 0);
+      sAxiWriteMasters : in  AxiWriteMasterArray(DMA_SIZE_G+1 downto 0);
+      sAxiWriteSlaves  : out AxiWriteSlaveArray(DMA_SIZE_G+1 downto 0);
+      sAxiReadMasters  : in  AxiReadMasterArray(DMA_SIZE_G+1 downto 0);
+      sAxiReadSlaves   : out AxiReadSlaveArray(DMA_SIZE_G+1 downto 0);
       -- Master
       mAxiWriteMaster  : out AxiWriteMasterType;
       mAxiWriteSlave   : in  AxiWriteSlaveType;
@@ -59,6 +59,16 @@ begin
       sAxiReadSlaves(i)  <= axiReadSlaves(i);
    end generate;
 
+   -- --------------------------------------------------------------
+   -- -- No resizing required for User General Purpose AXI Interface
+   -- --------------------------------------------------------------
+   -- axiWriteMasters(DMA_SIZE_G+1) <= sAxiWriteMasters(DMA_SIZE_G+1);
+   -- sAxiWriteSlaves(DMA_SIZE_G+1) <= axiWriteSlaves(DMA_SIZE_G+1);
+   -- axiReadMasters(DMA_SIZE_G+1)  <= sAxiReadMasters(DMA_SIZE_G+1);
+   -- sAxiReadSlaves(DMA_SIZE_G+1)  <= axiReadSlaves(DMA_SIZE_G+1);
+   sAxiWriteSlaves(DMA_SIZE_G+1) <= AXI_WRITE_SLAVE_FORCE_C;
+   sAxiReadSlaves(DMA_SIZE_G+1)  <= AXI_READ_SLAVE_FORCE_C;
+
    -------------------
    -- AXI XBAR IP Core
    -------------------

hardware/XilinxKcu105/xdc/XilinxKcu105App.xdc

@@ -8,16 +8,16 @@
 ## the terms contained in the LICENSE.txt file.
 ##############################################################################
 
-set_property -dict { PACKAGE_PIN AN8 IOSTANDARD LVCMOS18 } [get_ports { extRst }]
+set_property -dict { PACKAGE_PIN AN8 } [get_ports { extRst }]
 
-set_property -dict { PACKAGE_PIN AP8 IOSTANDARD LVCMOS18 } [get_ports { led[0] }]
-set_property -dict { PACKAGE_PIN H23 IOSTANDARD LVCMOS18 } [get_ports { led[1] }]
-set_property -dict { PACKAGE_PIN P20 IOSTANDARD LVCMOS18 } [get_ports { led[2] }]
-set_property -dict { PACKAGE_PIN P21 IOSTANDARD LVCMOS18 } [get_ports { led[3] }]
-set_property -dict { PACKAGE_PIN N22 IOSTANDARD LVCMOS18 } [get_ports { led[4] }]
-set_property -dict { PACKAGE_PIN M22 IOSTANDARD LVCMOS18 } [get_ports { led[5] }]
-set_property -dict { PACKAGE_PIN R23 IOSTANDARD LVCMOS18 } [get_ports { led[6] }]
-set_property -dict { PACKAGE_PIN P23 IOSTANDARD LVCMOS18 } [get_ports { led[7] }]
+set_property -dict { PACKAGE_PIN AP8 } [get_ports { led[0] }]
+set_property -dict { PACKAGE_PIN H23 } [get_ports { led[1] }]
+set_property -dict { PACKAGE_PIN P20 } [get_ports { led[2] }]
+set_property -dict { PACKAGE_PIN P21 } [get_ports { led[3] }]
+set_property -dict { PACKAGE_PIN N22 } [get_ports { led[4] }]
+set_property -dict { PACKAGE_PIN M22 } [get_ports { led[5] }]
+set_property -dict { PACKAGE_PIN R23 } [get_ports { led[6] }]
+set_property -dict { PACKAGE_PIN P23 } [get_ports { led[7] }]
 
 set_property PACKAGE_PIN W4 [get_ports sfpTxP[1]]
 set_property PACKAGE_PIN W3 [get_ports sfpTxN[1]]
@@ -32,20 +32,26 @@ set_property PACKAGE_PIN T1 [get_ports sfpRxN[0]]
 set_property PACKAGE_PIN P6 [get_ports sfpClk156P]
 set_property PACKAGE_PIN P5 [get_ports sfpClk156N]
 
-set_property -dict { PACKAGE_PIN J24 IOSTANDARD LVCMOS18 } [get_ports { fmcScl }]
-set_property -dict { PACKAGE_PIN J25 IOSTANDARD LVCMOS18 } [get_ports { fmcSda }]
+set_property -dict { PACKAGE_PIN J24 } [get_ports { fmcScl }]
+set_property -dict { PACKAGE_PIN J25 } [get_ports { fmcSda }]
 
 set_property -dict { PACKAGE_PIN AK17 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48 } [get_ports { sysClk300P }]
 set_property -dict { PACKAGE_PIN AK16 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48 } [get_ports { sysClk300N }]
 
-set_property PACKAGE_PIN R4 [get_ports { smaTxP }]
-set_property PACKAGE_PIN R3 [get_ports { smaTxN }]
+set_property PACKAGE_PIN R4 [get_ports { smaMgtTxP }]
+set_property PACKAGE_PIN R3 [get_ports { smaMgtTxN }]
 
-set_property PACKAGE_PIN P2 [get_ports { smaRxP }]
-set_property PACKAGE_PIN P1 [get_ports { smaRxN }]
+set_property PACKAGE_PIN P2 [get_ports { smaMgtRxP }]
+set_property PACKAGE_PIN P1 [get_ports { smaMgtRxN }]
 
-set_property PACKAGE_PIN V6 [get_ports { smaClkP }]
-set_property PACKAGE_PIN V5 [get_ports { smaClkN }]
+set_property PACKAGE_PIN V6 [get_ports { smaMgtClkP }]
+set_property PACKAGE_PIN V5 [get_ports { smaMgtClkN }]
+
+set_property PACKAGE_PIN D23 [get_ports { smaUserClkP }]
+set_property PACKAGE_PIN C23 [get_ports { smaUserClkN }]
+
+set_property PACKAGE_PIN H27 [get_ports { smaUserGpioP }]
+set_property PACKAGE_PIN G27 [get_ports { smaUserGpioN }]
 
 ##############################################################################
 

python/axipcie/_AxiGpuAsyncCore.py

@@ -1,4 +1,3 @@
-#!/usr/bin/env python
 #-----------------------------------------------------------------------------
 # This file is part of the 'axi-pcie-core'. It is subject to 
 # the license terms in the LICENSE.txt file found in the top-level directory 

python/axipcie/_AxiPcieCore.py

@@ -1,4 +1,3 @@
-#!/usr/bin/env python
 #-----------------------------------------------------------------------------
 # This file is part of the 'axi-pcie-core'. It is subject to 
 # the license terms in the LICENSE.txt file found in the top-level directory 

python/axipcie/_AxiPcieDma.py

@@ -1,3 +1,12 @@
+#-----------------------------------------------------------------------------
+# This file is part of the 'axi-pcie-core'. It is subject to 
+# the license terms in the LICENSE.txt file found in the top-level directory 
+# of this distribution and at: 
+#    https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. 
+# No part of the 'axi-pcie-core', including this file, may be 
+# copied, modified, propagated, or distributed except according to the terms 
+# contained in the LICENSE.txt file.
+#-----------------------------------------------------------------------------
 import rogue
 from collections import defaultdict
 

python/axipcie/_AxiPcieRoot.py

@@ -1,3 +1,12 @@
+#-----------------------------------------------------------------------------
+# This file is part of the 'axi-pcie-core'. It is subject to 
+# the license terms in the LICENSE.txt file found in the top-level directory 
+# of this distribution and at: 
+#    https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. 
+# No part of the 'axi-pcie-core', including this file, may be 
+# copied, modified, propagated, or distributed except according to the terms 
+# contained in the LICENSE.txt file.
+#-----------------------------------------------------------------------------
 import axipcie as pcie
 
 import pyrogue as pr

python/axipcie/_AxiPipCore.py

@@ -1,4 +1,3 @@
-#!/usr/bin/env python
 #-----------------------------------------------------------------------------
 # This file is part of the 'axi-pcie-core'. It is subject to 
 # the license terms in the LICENSE.txt file found in the top-level directory 

python/axipcie/_PcieAxiVersion.py

@@ -1,3 +1,12 @@
+#-----------------------------------------------------------------------------
+# This file is part of the 'axi-pcie-core'. It is subject to 
+# the license terms in the LICENSE.txt file found in the top-level directory 
+# of this distribution and at: 
+#    https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. 
+# No part of the 'axi-pcie-core', including this file, may be 
+# copied, modified, propagated, or distributed except according to the terms 
+# contained in the LICENSE.txt file.
+#-----------------------------------------------------------------------------
 import pyrogue              as pr
 import surf.axi             as axi 
 

python/axipcie/__init__.py

@@ -1,5 +1,12 @@
-#!/usr/bin/env python
-
+#-----------------------------------------------------------------------------
+# This file is part of the 'axi-pcie-core'. It is subject to 
+# the license terms in the LICENSE.txt file found in the top-level directory 
+# of this distribution and at: 
+#    https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. 
+# No part of the 'axi-pcie-core', including this file, may be 
+# copied, modified, propagated, or distributed except according to the terms 
+# contained in the LICENSE.txt file.
+#-----------------------------------------------------------------------------
 from axipcie._AxiGpuAsyncCore  import *
 from axipcie._AxiPcieCore    import *
 from axipcie._AxiPcieDma     import *

python/axipcie/updateFpga.py → scripts/updatePcieFpga

@@ -2,9 +2,6 @@
 #-----------------------------------------------------------------------------
 # Title      : BPI/SPIx4/SPIx8 Prom Update
 #-----------------------------------------------------------------------------
-# File       : updatePcieFpga.py
-# Created    : 2018-06-22
-#-----------------------------------------------------------------------------
 # This file is part of the 'axi-pcie-core'. It is subject to 
 # the license terms in the LICENSE.txt file found in the top-level directory 
 # of this distribution and at: 
@@ -21,15 +18,16 @@
 baseDir = os.path.dirname(os.path.realpath(__file__))
 
 print(f"Basedir = {baseDir}")
-pr.addLibraryPath(baseDir + '/..')
 
-# First see if surf is already in the python path
+# First see if surf and axipcie are already in the python path
 try:
     import surf
+    import axipcie
 
 # Otherwise assume it is relative in a standard development directory structure
 except:
-    pr.addLibraryPath(baseDir + '/../../../surf/python')
+    pr.addLibraryPath(baseDir + '/../python')
+    pr.addLibraryPath(baseDir + '/../../surf/python')
 
 import sys
 import glob