Merge pull request #150 from zeroasiccorp/update-sc

update to new SC

pyproject.toml

@@ -17,8 +17,8 @@ urls = {Homepage = "https://github.com/zeroasiccorp/umi"}
 requires-python = ">= 3.8"
 license = {file = "LICENSE"}
 dependencies = [
-    "siliconcompiler>=0.24.0",
-    "lambdalib>=0.2.4, <0.2.7"
+    "siliconcompiler>=0.26.0",
+    "lambdalib>=0.2.9, <0.2.10"
 ]
 dynamic = [
     "version"
@@ -29,7 +29,7 @@ version = {attr = "umi.__version__"}
 
 [project.optional-dependencies]
 test = [
-    "switchboard-hw",
+    "switchboard-hw>=0.2.14",
     "flake8==7.1.0"
 ]
 

umi/__init__.py

@@ -1,28 +1,11 @@
-from siliconcompiler import Library
-import lambdalib
+from umi import umi, lumi
 
 
 __version__ = "0.1.1"
 
 
-def _register_umi(lib):
-    lib.register_source("umi", "python://umi")
-
-
 def setup(chip):
-    libs = []
-
-    for name in ('umi', 'lumi'):
-        lib = Library(chip, name, package="umi")
-        _register_umi(lib)
-        lib.use(lambdalib)
-
-        lib.add("option", "idir", f"{name}/rtl")
-        lib.add("option", "ydir", f"{name}/rtl")
-
-        lib.add("option", "idir", "utils/rtl")
-        lib.add("option", "ydir", "utils/rtl")
-
-        libs.append(lib)
-
-    return libs
+    return [
+        umi.setup(chip),
+        lumi.setup(chip)
+    ]

umi/lumi/__init__.py

@@ -0,0 +1,21 @@
+from siliconcompiler import Library
+from umi import umi
+from lambdalib import auxlib, ramlib
+
+
+def setup(chip):
+    lib = Library(chip, "lumi", package="umi", auto_enable=True)
+    lib.register_source("umi", "python://umi")
+
+    lib.add("option", "idir", "lumi/rtl")
+    lib.add("option", "ydir", "lumi/rtl")
+
+    lib.add("option", "idir", "utils/rtl")
+    lib.add("option", "ydir", "utils/rtl")
+
+    lib.use(umi)
+
+    lib.use(auxlib)
+    lib.use(ramlib)
+
+    return lib

umi/lumi/rtl/lumi_rx.v

@@ -550,7 +550,7 @@ module lumi_rx
                       .CHAOS(0),         // generates random full logic when set
                       .CTRLW(1),         // width of asic ctrl interface
                       .TESTW(1),         // width of asic test interface
-                      .TYPE("DEFAULT"))  // Pass through variable for hard macro
+                      .PROP("DEFAULT"))  // Pass through variable for hard macro
         req_fifo_i(// Outputs
                    .wr_full          (req_fifo_full[j]),
                    .rd_dout          (req_fifo_dout[j*RXFIFOW+:RXFIFOW]),
@@ -598,7 +598,7 @@ module lumi_rx
                       .CHAOS(0),         // generates random full logic when set
                       .CTRLW(1),         // width of asic ctrl interface
                       .TESTW(1),         // width of asic test interface
-                      .TYPE("DEFAULT"))  // Pass through variable for hard macro
+                      .PROP("DEFAULT"))  // Pass through variable for hard macro
         resp_fifo_i(// Outputs
                     .wr_full          (resp_fifo_full[k]),
                     .rd_dout          (resp_fifo_dout[k*RXFIFOW+:RXFIFOW]),
@@ -663,7 +663,7 @@ module lumi_rx
                   .CHAOS(0),  // generates random full logic when set
                   .CTRLW(1),  // width of asic ctrl interface
                   .TESTW(1),  // width of asic test interface
-                  .TYPE("DEFAULT")) // Pass through variable for hard macro
+                  .PROP("DEFAULT")) // Pass through variable for hard macro
    lnk_fifo_i(// Outputs
               .wr_full          (),
               .rd_dout          (lnk_fifo_dout[CW-1:0]),
@@ -782,7 +782,7 @@ module lumi_rx
                   .CHAOS(0),              // generates random full logic when set
                   .CTRLW(1),              // width of asic ctrl interface
                   .TESTW(1),              // width of asic test interface
-                  .TYPE("DEFAULT"))       // Pass through variable for hard macro
+                  .PROP("DEFAULT"))       // Pass through variable for hard macro
    req_syncfifo_i(// Outputs
                   .wr_full          (sync_fifo_full[0]),
                   .rd_dout          (sync_fifo_dout[IOW-1:0]),
@@ -810,7 +810,7 @@ module lumi_rx
                   .CHAOS(0),              // generates random full logic when set
                   .CTRLW(1),              // width of asic ctrl interface
                   .TESTW(1),              // width of asic test interface
-                  .TYPE("DEFAULT"))       // Pass through variable for hard macro
+                  .PROP("DEFAULT"))       // Pass through variable for hard macro
    resp_syncfifo_i(// Outputs
                    .wr_full          (sync_fifo_full[1]),
                    .rd_dout          (sync_fifo_dout[2*IOW-1:IOW]),

umi/lumi/rtl/lumi_tx.v

@@ -597,7 +597,7 @@ module lumi_tx
                   .CHAOS(0),         // generates random full logic when set
                   .CTRLW(1),         // width of asic ctrl interface
                   .TESTW(1),         // width of asic test interface
-                  .TYPE("DEFAULT"))  // Pass through variable for hard macro
+                  .PROP("DEFAULT"))  // Pass through variable for hard macro
    phy_fifo_i(// Outputs
               .wr_full          (phy_fifo_full),
               .rd_dout          (phy_txdata[IOW-1:0]),

umi/lumi/testbench/test_lumi.py

@@ -9,7 +9,7 @@
 import numpy as np
 from argparse import ArgumentParser
 from switchboard import SbDut, UmiTxRx, delete_queue
-import umi
+from umi import lumi
 
 
 def build_testbench(topo="2d", trace=False):
@@ -24,11 +24,7 @@ def build_testbench(topo="2d", trace=False):
     else:
         raise ValueError('Invalid topology')
 
-    dut.use(umi)
-    dut.add('option', 'library', ['lumi', 'umi'])
-    dut.add('option', 'library', 'lambdalib_auxlib')
-    dut.add('option', 'library', 'lambdalib_ramlib')
-    dut.add('option', 'library', 'lambdalib_vectorlib')
+    dut.use(lumi)
 
     # Verilator configuration
     dut.set('tool', 'verilator', 'task', 'compile', 'file', 'config', 'lumi/testbench/config.vlt', package='umi')

umi/lumi/testbench/test_lumi_rnd.py

@@ -9,7 +9,7 @@
 import numpy as np
 from argparse import ArgumentParser
 from switchboard import SbDut, UmiTxRx, delete_queue
-import umi
+from umi import lumi
 
 
 def build_testbench(topo="2d", trace=False):
@@ -24,11 +24,7 @@ def build_testbench(topo="2d", trace=False):
     else:
         raise ValueError('Invalid topology')
 
-    dut.use(umi)
-    dut.add('option', 'library', ['lumi', 'umi'])
-    dut.add('option', 'library', 'lambdalib_auxlib')
-    dut.add('option', 'library', 'lambdalib_ramlib')
-    dut.add('option', 'library', 'lambdalib_vectorlib')
+    dut.use(lumi)
 
     # Verilator configuration
     dut.set('tool', 'verilator', 'task', 'compile', 'file', 'config', 'lumi/testbench/config.vlt', package='umi')

umi/umi/__init__.py

@@ -0,0 +1,19 @@
+from siliconcompiler import Library
+from lambdalib import auxlib, ramlib, vectorlib
+
+
+def setup(chip):
+    lib = Library(chip, "umi", package="umi", auto_enable=True)
+    lib.register_source("umi", "python://umi")
+
+    lib.add("option", "idir", "umi/rtl")
+    lib.add("option", "ydir", "umi/rtl")
+
+    lib.add("option", "idir", "utils/rtl")
+    lib.add("option", "ydir", "utils/rtl")
+
+    lib.use(auxlib)
+    lib.use(ramlib)
+    lib.use(vectorlib)
+
+    return lib

umi/umi/rtl/umi_mem_agent.v

@@ -260,7 +260,7 @@ module umi_mem_agent
 
    la_spram #(.DW    (DW),               // Memory width
               .AW    ($clog2(RAMDEPTH)), // Address width (derived)
-              .TYPE  (SRAMTYPE),         // Pass through variable for hard macro
+              .PROP  (SRAMTYPE),         // Pass through variable for hard macro
               .CTRLW (CTRLW),            // Width of asic ctrl interface
               .TESTW (128)               // Width of asic test interface
               )

umi/umi/testbench/test_crossbar.py

@@ -8,7 +8,7 @@
 import numpy as np
 from argparse import ArgumentParser
 from switchboard import UmiTxRx, random_umi_packet, delete_queue, verilator_run, SbDut
-import umi
+from umi import umi
 
 
 def build_testbench():
@@ -18,10 +18,6 @@ def build_testbench():
     dut.input('umi/testbench/testbench_crossbar.sv', package='umi')
 
     dut.use(umi)
-    dut.add('option', 'library', 'umi')
-    dut.add('option', 'library', 'lambdalib_auxlib')
-    dut.add('option', 'library', 'lambdalib_ramlib')
-    dut.add('option', 'library', 'lambdalib_vectorlib')
 
     # Verilator configuration
     dut.set('tool', 'verilator', 'task', 'compile', 'file', 'config', 'umi/testbench/config.vlt', package='umi')

umi/umi/testbench/test_fifo.py

@@ -7,7 +7,7 @@
 import numpy as np
 from argparse import ArgumentParser
 from switchboard import SbDut, UmiTxRx, delete_queue, verilator_run
-import umi
+from umi import umi
 
 
 def build_testbench():
@@ -17,9 +17,6 @@ def build_testbench():
     dut.input('umi/testbench/testbench_fifo.sv', package='umi')
 
     dut.use(umi)
-    dut.add('option', 'library', 'umi')
-    dut.add('option', 'library', 'lambdalib_auxlib')
-    dut.add('option', 'library', 'lambdalib_ramlib')
 
     # Verilator configuration
     dut.set('tool', 'verilator', 'task', 'compile', 'file', 'config', 'umi/testbench/config.vlt', package='umi')

umi/umi/testbench/test_fifo_flex.py

@@ -7,7 +7,7 @@
 import numpy as np
 from argparse import ArgumentParser
 from switchboard import SbDut, UmiTxRx, delete_queue, verilator_run
-import umi
+from umi import umi
 
 
 def build_testbench(split=False):
@@ -17,9 +17,6 @@ def build_testbench(split=False):
     dut.input('umi/testbench/testbench_fifo_flex.sv', package='umi')
 
     dut.use(umi)
-    dut.add('option', 'library', 'umi')
-    dut.add('option', 'library', 'lambdalib_auxlib')
-    dut.add('option', 'library', 'lambdalib_ramlib')
 
     dut.add('option', 'define', f'SPLIT={int(split)}')
 

umi/umi/testbench/test_mem_agent.py

@@ -6,7 +6,7 @@
 import numpy as np
 from argparse import ArgumentParser
 from switchboard import SbDut, UmiTxRx, delete_queue, verilator_run
-import umi
+from umi import umi
 
 
 def build_testbench():
@@ -16,9 +16,6 @@ def build_testbench():
     dut.input('umi/testbench/testbench_mem_agent.sv', package='umi')
 
     dut.use(umi)
-    dut.add('option', 'library', 'umi')
-    dut.add('option', 'library', 'lambdalib_auxlib')
-    dut.add('option', 'library', 'lambdalib_ramlib')
 
     # Verilator configuration
     dut.set('tool', 'verilator', 'task', 'compile', 'file', 'config', 'umi/testbench/config.vlt', package='umi')

umi/umi/testbench/test_regif.py

@@ -7,7 +7,7 @@
 import numpy as np
 from argparse import ArgumentParser
 from switchboard import SbDut, UmiTxRx, delete_queue, verilator_run
-import umi
+from umi import umi
 
 
 def build_testbench():
@@ -17,8 +17,6 @@ def build_testbench():
     dut.input('umi/testbench/testbench_regif.sv', package='umi')
 
     dut.use(umi)
-    dut.add('option', 'library', 'umi')
-    dut.add('option', 'library', 'lambdalib_ramlib')
 
     # Verilator configuration
     dut.set('tool', 'verilator', 'task', 'compile', 'file', 'config', 'umi/testbench/config.vlt', package='umi')

umi/umi/testbench/test_umi_ram.py

@@ -6,7 +6,7 @@
 import numpy as np
 from argparse import ArgumentParser
 from switchboard import SbDut, UmiTxRx, verilator_run
-import umi
+from umi import umi
 
 
 def build_testbench():
@@ -16,10 +16,6 @@ def build_testbench():
     dut.input('umi/testbench/testbench_umi_ram.sv', package='umi')
 
     dut.use(umi)
-    dut.add('option', 'library', 'umi')
-    dut.add('option', 'library', 'lambdalib_auxlib')
-    dut.add('option', 'library', 'lambdalib_ramlib')
-    dut.add('option', 'library', 'lambdalib_vectorlib')
 
     # Verilator configuration
     dut.set('tool', 'verilator', 'task', 'compile', 'file', 'config', 'umi/testbench/config.vlt', package='umi')

umi/utils/rtl/tl2umi_np.v

@@ -468,7 +468,7 @@ module tl2umi_np #(
     la_syncfifo #(
         .DW     (CW + AW + AW + DW),
         .DEPTH  (2),
-        .TYPE   ("DEFAULT")
+        .PROP   ("DEFAULT")
     ) tl2umi_req_fifo (
         .clk        (clk),
         .nreset     (nreset),

umi/utils/testbench/test_tl2umi_np.py

@@ -3,7 +3,7 @@
 from siliconcompiler import Chip
 from siliconcompiler.flows import dvflow
 from siliconcompiler.package import path as sc_path
-import umi
+from umi import umi
 
 
 def build():
@@ -15,11 +15,6 @@ def build():
 
     chip.input('utils/testbench/tb_tl2umi_np.v', package='umi')
 
-    chip.add('option', 'library', 'umi')
-    chip.add('option', 'library', 'lambdalib_auxlib')
-    chip.add('option', 'library', 'lambdalib_ramlib')
-    chip.add('option', 'library', 'lambdalib_vectorlib')
-
     memfile = f"{sc_path(chip, 'umi')}/utils/testbench/buffer.memh"
 
     chip.add('tool', 'execute', 'task', 'exec_input', 'option', f'+MEMHFILE={memfile}')

umi/utils/testbench/test_umi2apb.py

@@ -6,16 +6,14 @@
 import random
 import numpy as np
 from switchboard import SbDut, UmiTxRx, verilator_run
-import umi
+from umi import umi
 
 
 def build_testbench(dut):
     # Set up inputs
     dut.input('utils/testbench/testbench_umi2apb.sv', package='umi')
 
     dut.use(umi)
-    dut.add('option', 'library', 'umi')
-    dut.add('option', 'library', 'lambdalib_ramlib')
 
     # Verilator configuration
     dut.set('tool', 'verilator', 'task', 'compile', 'file', 'config', 'utils/testbench/config.vlt',

umi/utils/testbench/test_umi2axilite.py

@@ -7,7 +7,7 @@
 import numpy as np
 from argparse import ArgumentParser
 from switchboard import SbDut, UmiTxRx, delete_queue, verilator_run
-import umi
+from umi import umi
 
 
 def build_testbench():
@@ -17,10 +17,6 @@ def build_testbench():
     dut.input('utils/testbench/testbench_umi2axilite.sv', package='umi')
 
     dut.use(umi)
-    dut.add('option', 'library', 'umi')
-    dut.add('option', 'library', 'lambdalib_ramlib')
-    dut.add('option', 'library', 'lambdalib_auxlib')
-    dut.add('option', 'library', 'lambdalib_vectorlib')
 
     # Verilator configuration
     dut.set('tool', 'verilator', 'task', 'compile', 'file', 'config',