Skip to content

Commit

Permalink
remove trace by default
Browse files Browse the repository at this point in the history
  • Loading branch information
@gadfort
gadfort committed Jul 9, 2024
1 parent 24c385d commit 8e42359
Show file tree
Hide file tree
Showing 12 changed files with 12 additions and 23 deletions.
3 changes: 1 addition & 2 deletions umi/lumi/testbench/test_lumi.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,7 @@


def build_testbench(topo="2d", trace=False):
dut = SbDut('testbench', trace=False, trace_type='fst', default_main=True)
dut = SbDut('testbench', trace=trace, trace_type='fst', default_main=True)

# Set up inputs
dut.input('lumi/testbench/testbench_lumi.sv', package='umi')
Expand All @@ -39,7 +39,6 @@ def build_testbench(topo="2d", trace=False):
dut.add('tool', 'verilator', 'task', 'compile', 'option', '-Wall')

# Settings - enable tracing
dut.set('option', 'trace', False)
dut.set('tool', 'verilator', 'task', 'compile', 'var', 'trace_type', 'fst')

# Build simulator
Expand Down
2 changes: 1 addition & 1 deletion umi/lumi/testbench/test_lumi_rnd.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,7 @@


def build_testbench(topo="2d", trace=False):
dut = SbDut('testbench', trace=False, trace_type='fst', default_main=True)
dut = SbDut('testbench', trace=trace, trace_type='fst', default_main=True)

# Set up inputs
dut.input('lumi/testbench/testbench_lumi.sv', package='umi')
Expand Down
3 changes: 1 addition & 2 deletions umi/umi/testbench/test_crossbar.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -12,7 +12,7 @@


def build_testbench():
dut = SbDut('testbench', default_main=True)
dut = SbDut('testbench', trace=False, default_main=True)

# Set up inputs
dut.input('umi/testbench/testbench_crossbar.sv', package='umi')
Expand All @@ -31,7 +31,6 @@ def build_testbench():
dut.add('tool', 'verilator', 'task', 'compile', 'option', '-Wall')

# Settings - enable tracing
dut.set('option', 'trace', False)
dut.set('tool', 'verilator', 'task', 'compile', 'var', 'trace_type', 'fst')

# Build simulator
Expand Down
3 changes: 1 addition & 2 deletions umi/umi/testbench/test_fifo.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,7 @@


def build_testbench():
dut = SbDut('testbench', default_main=True)
dut = SbDut('testbench', trace=False, default_main=True)

# Set up inputs
dut.input('umi/testbench/testbench_fifo.sv', package='umi')
Expand All @@ -30,7 +30,6 @@ def build_testbench():
dut.add('tool', 'verilator', 'task', 'compile', 'option', '-Wall')

# Settings - enable tracing
dut.set('option', 'trace', False)
dut.set('tool', 'verilator', 'task', 'compile', 'var', 'trace_type', 'fst')

# Build simulator
Expand Down
3 changes: 1 addition & 2 deletions umi/umi/testbench/test_fifo_flex.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,7 @@


def build_testbench(split=False):
dut = SbDut('testbench', default_main=True)
dut = SbDut('testbench', trace=False, default_main=True)

# Set up inputs
dut.input('umi/testbench/testbench_fifo_flex.sv', package='umi')
Expand All @@ -32,7 +32,6 @@ def build_testbench(split=False):
dut.add('tool', 'verilator', 'task', 'compile', 'option', '-Wall')

# Settings - enable tracing
dut.set('option', 'trace', False)
dut.set('tool', 'verilator', 'task', 'compile', 'var', 'trace_type', 'fst')

# Build simulator
Expand Down
3 changes: 1 addition & 2 deletions umi/umi/testbench/test_mem_agent.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -10,7 +10,7 @@


def build_testbench():
dut = SbDut('testbench', default_main=True)
dut = SbDut('testbench', trace=False, default_main=True)

# Set up inputs
dut.input('umi/testbench/testbench_mem_agent.sv', package='umi')
Expand All @@ -29,7 +29,6 @@ def build_testbench():
dut.add('tool', 'verilator', 'task', 'compile', 'option', '-Wall')

# Settings - enable tracing
dut.set('option', 'trace', False)
dut.set('tool', 'verilator', 'task', 'compile', 'var', 'trace_type', 'fst')

# Build simulator
Expand Down
3 changes: 1 addition & 2 deletions umi/umi/testbench/test_regif.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,7 @@


def build_testbench():
dut = SbDut('testbench', default_main=True)
dut = SbDut('testbench', trace=False, default_main=True)

# Set up inputs
dut.input('umi/testbench/testbench_regif.sv', package='umi')
Expand All @@ -29,7 +29,6 @@ def build_testbench():
dut.add('tool', 'verilator', 'task', 'compile', 'option', '-Wall')

# Settings - enable tracing
dut.set('option', 'trace', False)
dut.set('tool', 'verilator', 'task', 'compile', 'var', 'trace_type', 'fst')

# Build simulator
Expand Down
3 changes: 1 addition & 2 deletions umi/umi/testbench/test_umi_ram.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -10,7 +10,7 @@


def build_testbench():
dut = SbDut('testbench', default_main=True)
dut = SbDut('testbench', trace=False, default_main=True)

# Set up inputs
dut.input('umi/testbench/testbench_umi_ram.sv', package='umi')
Expand All @@ -30,7 +30,6 @@ def build_testbench():
dut.add('tool', 'verilator', 'task', 'compile', 'option', '-Wall')

# Settings - enable tracing
dut.set('option', 'trace', False)
dut.set('tool', 'verilator', 'task', 'compile', 'var', 'trace_type', 'fst')

# Build simulator
Expand Down
3 changes: 1 addition & 2 deletions umi/utils/testbench/test_umi2axilite.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,7 @@


def build_testbench():
dut = SbDut('testbench', default_main=True)
dut = SbDut('testbench', trace=False, default_main=True)

# Set up inputs
dut.input('utils/testbench/testbench_umi2axilite.sv', package='umi')
Expand All @@ -29,7 +29,6 @@ def build_testbench():
dut.add('tool', 'verilator', 'task', 'compile', 'option', '-Wall')

# Settings - enable tracing
dut.set('option', 'trace', False)
dut.set('tool', 'verilator', 'task', 'compile', 'var', 'trace_type', 'fst')

# Build simulator
Expand Down
3 changes: 1 addition & 2 deletions umi/utils/testbench/test_umi2tl_np.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -12,7 +12,7 @@


def build_testbench(topo="2d"):
dut = SbDut('testbench', default_main=False)
dut = SbDut('testbench', trace=False, default_main=False)

# Set up inputs
if topo == '2d':
Expand All @@ -39,7 +39,6 @@ def build_testbench(topo="2d"):
dut.add('tool', 'verilator', 'task', 'compile', 'option', '-Wall')

# Settings - enable tracing
dut.set('option', 'trace', False)
dut.set('tool', 'verilator', 'task', 'compile', 'var', 'trace_type', 'fst')

# Build simulator
Expand Down
3 changes: 1 addition & 2 deletions umi/utils/testbench/test_umi_address_remap.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,7 @@


def build_testbench(topo="2d"):
dut = SbDut('testbench', default_main=True)
dut = SbDut('testbench', trace=False, default_main=True)

# Set up inputs
if topo == '2d':
Expand All @@ -30,7 +30,6 @@ def build_testbench(topo="2d"):
dut.add('tool', 'verilator', 'task', 'compile', 'option', '-Wall')

# Settings - enable tracing
dut.set('option', 'trace', False)
dut.set('tool', 'verilator', 'task', 'compile', 'var', 'trace_type', 'fst')

# Build simulator
Expand Down
3 changes: 1 addition & 2 deletions umi/utils/testbench/test_umi_packet_merge_greedy.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@


def build_testbench(topo="2d"):
dut = SbDut('testbench', default_main=False)
dut = SbDut('testbench', trace=False, default_main=False)

# Set up inputs
if topo == '2d':
Expand All @@ -32,7 +32,6 @@ def build_testbench(topo="2d"):
dut.add('tool', 'verilator', 'task', 'compile', 'option', '-Wall')

# Settings - enable tracing
dut.set('option', 'trace', False)
dut.set('tool', 'verilator', 'task', 'compile', 'var', 'trace_type', 'fst')

# Build simulator
Expand Down

0 comments on commit 8e42359

Please sign in to comment.