Ali/umi fifo flex merge

umi/testbench/test_fifo_flex.py

@@ -65,16 +65,16 @@ def main(vldmode="2", rdymode="2", host2dut="host2dut_0.q", dut2host="dut2host_0
 
     print("### Statring test ###")
 
-    for count in range (100):
+    for count in range (1000):
         # length should not cross the DW boundary - umi_mem_agent limitation
-        length = np.random.randint(0,15)
+        length = np.random.randint(0,255)
         dst_addr = 32*random.randrange(2**(10-5)-1) # sb limitation - should align to bus width
         src_addr = 32*random.randrange(2**(10-5)-1)
         data8 = np.random.randint(0,255,size=length,dtype=np.uint8)
-        print(f"umi writing {length+1} bytes to addr 0x{dst_addr:08x}")
-        host.write(dst_addr, data8, srcaddr=src_addr)
-        print(f"umi read from addr 0x{dst_addr:08x}")
-        val8 = host.read(dst_addr, length, np.uint8, srcaddr=src_addr)
+        print(f"[{count}] umi writing {length} bytes to addr 0x{dst_addr:08x}")
+        host.write(dst_addr, data8, srcaddr=src_addr, max_bytes=16)
+        print(f"[{count}] umi read from addr 0x{dst_addr:08x}")
+        val8 = host.read(dst_addr, length, np.uint8, srcaddr=src_addr, max_bytes=16)
         if ~((val8 == data8).all()):
             print(f"ERROR umi read from addr 0x{dst_addr:08x}")
             print(f"Expected:")

umi/testbench/testbench_fifo_flex.sv

@@ -51,7 +51,7 @@ module testbench (
    wire [AW-1:0]        umi_resp_in_srcaddr;
    wire                 umi_resp_in_valid;
    // End of automatics
-   reg                  nreset;
+   wire                 nreset;
 
    wire [CTRLW-1:0]     sram_ctrl = 8'b0;
 
@@ -86,10 +86,10 @@ module testbench (
                   );
 
    umi_tx_sim #(.READY_MODE_DEFAULT(2),
-                .DW(ODW)
+                .DW(IDW)
                 )
    host_umi_tx_i (.clk(clk),
-                  .data(umi_resp_out_data[ODW-1:0]),
+                  .data(umi_resp_out_data[IDW-1:0]),
                   .srcaddr(umi_resp_out_srcaddr[AW-1:0]),
                   .dstaddr(umi_resp_out_dstaddr[AW-1:0]),
                   .cmd(umi_resp_out_cmd[CW-1:0]),
@@ -238,14 +238,17 @@ module testbench (
 
    // VCD
 
+   reg [15:0] nreset_r;
+   assign nreset = ~nreset_r[15];
+
    initial
      begin
-        nreset   = 1'b0;
+        nreset_r = 16'hFFFF;
      end // initial begin
 
    always @(negedge clk)
      begin
-        nreset <= nreset | 1'b1;
+        nreset_r <= nreset_r << 1;
      end
 
    // control block
@@ -260,7 +263,7 @@ module testbench (
 
    // auto-stop
 
-   auto_stop_sim #(.CYCLES(50000)) auto_stop_sim_i (.clk(clk));
+   auto_stop_sim #(.CYCLES(500000)) auto_stop_sim_i (.clk(clk));
 
 endmodule
 // Local Variables:

utils/rtl/umi2tl_np.v

@@ -170,7 +170,7 @@ module umi2tl_np #(
     );
 
     // Calculate byte shift needed
-    wire [$clog2(ODW/8):0] req_bytes = (1 << fifoflex_out_req_cmd_size)*(fifoflex_out_req_cmd_len + 1);
+    wire [7:0] req_bytes = (1 << fifoflex_out_req_cmd_size)*(fifoflex_out_req_cmd_len + 1);
 
     reg [2:0]   masked_shift;
     reg [2:0]   masked_tl_a_size;

utils/rtl/umi_packet_merge_greedy.v

@@ -148,7 +148,7 @@ module umi_packet_merge_greedy #(
     wire                    umi_in_ready_r;
     wire                    umi_in_cmd_commit_r;
 
-    reg [$clog2(ODW/8):0]   byte_counter;
+    reg [7:0]               byte_counter;
     localparam [$clog2(ODW/8):0]    ODW_BYTES = ODW[3+$clog2(ODW/8):3];
     localparam                      ADDR_PAD_BYTES = AW - 1 - $clog2(ODW/8);
 
@@ -236,9 +236,9 @@ module umi_packet_merge_greedy #(
     wire                    umi_in_opcode_check;
     wire                    umi_in_field_match;
     wire                    umi_in_mergeable;
-    wire [$clog2(IDW/8):0]  umi_in_bytes;
+    wire [7:0]              umi_in_bytes;
     reg                     umi_in_mergeable_r;
-    reg  [$clog2(IDW/8):0]  umi_in_bytes_r;
+    reg  [7:0]              umi_in_bytes_r;
 
     reg [AW-1:0]            umi_in_dstaddr_nx;
     reg [AW-1:0]            umi_in_srcaddr_nx;

utils/testbench/config.vlt

@@ -18,5 +18,5 @@ lint_off -rule BLKSEQ -file "*switchboard/switchboard/verilog/*"
 lint_off -rule GENUNNAMED
 lint_off -rule TIMESCALEMOD
 // To be fixed:
-lint_off -rule SYNCASYNCNET
-lint_off -rule WIDTHTRUNC
+//lint_off -rule SYNCASYNCNET
+//lint_off -rule WIDTHTRUNC

utils/testbench/testbench_umi2tl_np.v

@@ -50,7 +50,7 @@ module testbench #(
 
     // Reset initialization
     always @(posedge clk) begin
-        nreset_vec <= {nreset_vec[15:0], 1'b1};
+        nreset_vec <= {nreset_vec[14:0], 1'b1};
     end
 
     assign nreset = nreset_vec[14];

utils/testbench/testbench_umi_packet_merge_greedy.v

@@ -56,7 +56,7 @@ module testbench #(
     wire [ODW-1:0]  umi_dut2check_data;
     reg             umi_dut2check_ready;
 
-    always @(posedge clk) begin
+    always @(posedge clk or negedge nreset) begin
         if(~nreset)
             umi_dut2check_ready <= 1'b0;
         else