Ali/umi fifo flex merge

utils/rtl/umi2tl_np.v

@@ -170,7 +170,9 @@ module umi2tl_np #(
     );
 
     // Calculate byte shift needed
+    /* verilator lint_off WIDTHTRUNC */
     wire [$clog2(ODW/8):0] req_bytes = (1 << fifoflex_out_req_cmd_size)*(fifoflex_out_req_cmd_len + 1);
+    /* verilator lint_on WIDTHTRUNC */
 
     reg [2:0]   masked_shift;
     reg [2:0]   masked_tl_a_size;

utils/rtl/umi_packet_merge_greedy.v

@@ -266,7 +266,9 @@ module umi_packet_merge_greedy #(
                               umi_in_opcode_check &
                               umi_in_field_match;
 
+    /* verilator lint_off WIDTHTRUNC */
     assign umi_in_bytes = (1 << umi_in_cmd_size)*(umi_in_cmd_len + 1);
+    /* verilator lint_on WIDTHTRUNC */
 
     always @(posedge clk or negedge nreset) begin
         if (~nreset)

utils/testbench/config.vlt

@@ -18,5 +18,5 @@ lint_off -rule BLKSEQ -file "*switchboard/switchboard/verilog/*"
 lint_off -rule GENUNNAMED
 lint_off -rule TIMESCALEMOD
 // To be fixed:
-lint_off -rule SYNCASYNCNET
-lint_off -rule WIDTHTRUNC
+//lint_off -rule SYNCASYNCNET
+//lint_off -rule WIDTHTRUNC

utils/testbench/testbench_umi2tl_np.v

@@ -50,7 +50,7 @@ module testbench #(
 
     // Reset initialization
     always @(posedge clk) begin
-        nreset_vec <= {nreset_vec[15:0], 1'b1};
+        nreset_vec <= {nreset_vec[14:0], 1'b1};
     end
 
     assign nreset = nreset_vec[14];

utils/testbench/testbench_umi_packet_merge_greedy.v

@@ -56,7 +56,7 @@ module testbench #(
     wire [ODW-1:0]  umi_dut2check_data;
     reg             umi_dut2check_ready;
 
-    always @(posedge clk) begin
+    always @(posedge clk or negedge nreset) begin
         if(~nreset)
             umi_dut2check_ready <= 1'b0;
         else