DCC

The HCLK duty cycle correction module (DCC) is a primitive that corrects the duty cycle of an input clock signal, as indicated by its name. Its ports include DCCCLKIN for the input clock and CLKOUT for the output corrected clock. The specific details about the supported devices, such as the LittleBee GW1N and GW1NR series, are provided in another section of the document, suggesting that the primary function of the DCC primitive is to correct the duty cycle of a clock signal.

This device is not yet supported in Apicula

Ports

Port	Size	Direction
CLKIN	1	input
CLKOUT	1	output

Parameters

Parameter	Default Value
DCC_EN	1 (0b1)

Verilog Instantiation

DCC #(
    .DCC_EN(DCC_EN)
) dcc_inst (
    .CLKIN(CLKIN),
    .CLKOUT(CLKOUT)
);