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MIPI
Pepijn de Vos edited this page Nov 19, 2024
·
2 revisions
This device is not yet supported in Apicula
| Port | Size | Direction |
|---|---|---|
| ARSTN_TX | 1 | input |
| ARST_RXLN0 | 1 | input |
| ARST_RXLN1 | 1 | input |
| ARST_RXLN2 | 1 | input |
| D0A | 1 | inout |
| D0B | 1 | inout |
| D0C | 1 | inout |
| D0LN_HSRXD | 42 | output |
| D0LN_HSRXD_VLD | 1 | output |
| D0LN_HSRX_DEMAP_INVLD | 2 | output |
| D0LN_HSRX_EN | 1 | input |
| D0LN_HSRX_FIFO_RDE_ERR | 1 | output |
| D0LN_HSRX_FIFO_WRF_ERR | 1 | output |
| D0LN_HSRX_WA | 2 | output |
| D0LN_HSTX_DATA | 42 | input |
| D0LN_HSTX_DATA_VLD | 1 | input |
| D0LN_HSTX_EN | 1 | input |
| D0LN_HSTX_MAP_DIS | 2 | input |
| D0LN_RX_CLK_1X_I | 1 | input |
| D0LN_RX_CLK_1X_O | 1 | output |
| D0LN_RX_DRST_N | 1 | input |
| D0LN_TX_DRST_N | 1 | input |
| D1A | 1 | inout |
| D1B | 1 | inout |
| D1C | 1 | inout |
| D1LN_HSRXD | 42 | output |
| D1LN_HSRXD_VLD | 1 | output |
| D1LN_HSRX_DEMAP_INVLD | 2 | output |
| D1LN_HSRX_EN | 1 | input |
| D1LN_HSRX_FIFO_RDE_ERR | 1 | output |
| D1LN_HSRX_FIFO_WRF_ERR | 1 | output |
| D1LN_HSRX_WA | 2 | output |
| D1LN_HSTX_DATA | 42 | input |
| D1LN_HSTX_DATA_VLD | 1 | input |
| D1LN_HSTX_EN | 1 | input |
| D1LN_HSTX_MAP_DIS | 2 | input |
| D1LN_RX_CLK_1X_I | 1 | input |
| D1LN_RX_CLK_1X_O | 1 | output |
| D1LN_RX_DRST_N | 1 | input |
| D1LN_TX_DRST_N | 1 | input |
| D2A | 1 | inout |
| D2B | 1 | inout |
| D2C | 1 | inout |
| D2LN_HSRXD | 42 | output |
| D2LN_HSRXD_VLD | 1 | output |
| D2LN_HSRX_DEMAP_INVLD | 2 | output |
| D2LN_HSRX_EN | 1 | input |
| D2LN_HSRX_FIFO_RDE_ERR | 1 | output |
| D2LN_HSRX_FIFO_WRF_ERR | 1 | output |
| D2LN_HSRX_WA | 2 | output |
| D2LN_HSTX_DATA | 42 | input |
| D2LN_HSTX_DATA_VLD | 1 | input |
| D2LN_HSTX_EN | 1 | input |
| D2LN_HSTX_MAP_DIS | 2 | input |
| D2LN_RX_CLK_1X_I | 1 | input |
| D2LN_RX_CLK_1X_O | 1 | output |
| D2LN_RX_DRST_N | 1 | input |
| D2LN_TX_DRST_N | 1 | input |
| DI_LPRX0_A | 1 | output |
| DI_LPRX0_B | 1 | output |
| DI_LPRX0_C | 1 | output |
| DI_LPRX1_A | 1 | output |
| DI_LPRX1_B | 1 | output |
| DI_LPRX1_C | 1 | output |
| DI_LPRX2_A | 1 | output |
| DI_LPRX2_B | 1 | output |
| DI_LPRX2_C | 1 | output |
| DO_LPTX_A_LN0 | 1 | input |
| DO_LPTX_A_LN1 | 1 | input |
| DO_LPTX_A_LN2 | 1 | input |
| DO_LPTX_B_LN0 | 1 | input |
| DO_LPTX_B_LN1 | 1 | input |
| DO_LPTX_B_LN2 | 1 | input |
| DO_LPTX_C_LN0 | 1 | input |
| DO_LPTX_C_LN1 | 1 | input |
| DO_LPTX_C_LN2 | 1 | input |
| GPLL_CK0 | 1 | input |
| GPLL_CK180 | 1 | input |
| GPLL_CK270 | 1 | input |
| GPLL_CK90 | 1 | input |
| HSRX_EN_D0 | 1 | input |
| HSRX_EN_D1 | 1 | input |
| HSRX_EN_D2 | 1 | input |
| HSRX_ODT_EN_D0 | 1 | input |
| HSRX_ODT_EN_D1 | 1 | input |
| HSRX_ODT_EN_D2 | 1 | input |
| HSTX_ENLN0 | 1 | input |
| HSTX_ENLN1 | 1 | input |
| HSTX_ENLN2 | 1 | input |
| HSTX_FIFO_AE | 1 | output |
| HSTX_FIFO_AF | 1 | output |
| HSTX_FIFO_RDE_ERR | 1 | output |
| HSTX_FIFO_WRF_ERR | 1 | output |
| LPRX_EN_D0 | 1 | input |
| LPRX_EN_D1 | 1 | input |
| LPRX_EN_D2 | 1 | input |
| LPTX_ENLN0 | 1 | input |
| LPTX_ENLN1 | 1 | input |
| LPTX_ENLN2 | 1 | input |
| MDRP_A_D_I | 8 | input |
| MDRP_A_INC_I | 1 | input |
| MDRP_CLK_I | 1 | input |
| MDRP_OPCODE_I | 2 | input |
| MDRP_RDATA | 8 | output |
| PWRON_RX_LN0 | 1 | input |
| PWRON_RX_LN1 | 1 | input |
| PWRON_RX_LN2 | 1 | input |
| PWRON_TX | 1 | input |
| RX_CLK_EN_LN0 | 1 | input |
| RX_CLK_EN_LN1 | 1 | input |
| RX_CLK_EN_LN2 | 1 | input |
| RX_CLK_MUXED | 1 | output |
| SPLL0_CKN | 1 | input |
| SPLL0_CKP | 1 | input |
| SPLL1_CKN | 1 | input |
| SPLL1_CKP | 1 | input |
| TXDP_ENLN0 | 1 | input |
| TXDP_ENLN1 | 1 | input |
| TXDP_ENLN2 | 1 | input |
| TXHCLK_EN | 1 | input |
| TX_CLK_1X_I | 1 | input |
| TX_CLK_1X_O | 1 | output |
| Parameter | Default Value |
|---|---|
| CLK_SEL | 0 (0b00) |
| D0LN_HS_RX_EN | 1 (0b1) |
| D0LN_HS_TX_EN | 1 (0b1) |
| D0LN_RX_HS_21BIT_MODE | 0 (0b0) |
| D0LN_RX_REASGN_A | 0 (0b00) |
| D0LN_RX_REASGN_B | 1 (0b01) |
| D0LN_RX_REASGN_C | 2 (0b10) |
| D0LN_RX_WA_SYNC_PAT0_EN | 1 (0b1) |
| D0LN_RX_WA_SYNC_PAT0_H | 73 (0b1001001) |
| D0LN_RX_WA_SYNC_PAT0_L | 36 (0b00100100) |
| D0LN_RX_WA_SYNC_PAT1_EN | 1 (0b1) |
| D0LN_RX_WA_SYNC_PAT1_H | 41 (0b0101001) |
| D0LN_RX_WA_SYNC_PAT1_L | 36 (0b00100100) |
| D0LN_RX_WA_SYNC_PAT2_EN | 1 (0b1) |
| D0LN_RX_WA_SYNC_PAT2_H | 25 (0b0011001) |
| D0LN_RX_WA_SYNC_PAT2_L | 36 (0b00100100) |
| D0LN_RX_WA_SYNC_PAT3_EN | 0 (0b0) |
| D0LN_RX_WA_SYNC_PAT3_H | 9 (0b0001001) |
| D0LN_RX_WA_SYNC_PAT3_L | 36 (0b00100100) |
| D0LN_RX_W_LENDIAN | 1 (0b1) |
| D0LN_TX_REASGN_A | 0 (0b00) |
| D0LN_TX_REASGN_B | 1 (0b01) |
| D0LN_TX_REASGN_C | 2 (0b10) |
| D1LN_HS_RX_EN | 1 (0b1) |
| D1LN_HS_TX_EN | 1 (0b1) |
| D1LN_RX_HS_21BIT_MODE | 0 (0b0) |
| D1LN_RX_REASGN_A | 0 (0b00) |
| D1LN_RX_REASGN_B | 1 (0b01) |
| D1LN_RX_REASGN_C | 2 (0b10) |
| D1LN_RX_WA_SYNC_PAT0_EN | 1 (0b1) |
| D1LN_RX_WA_SYNC_PAT0_H | 73 (0b1001001) |
| D1LN_RX_WA_SYNC_PAT0_L | 36 (0b00100100) |
| D1LN_RX_WA_SYNC_PAT1_EN | 1 (0b1) |
| D1LN_RX_WA_SYNC_PAT1_H | 41 (0b0101001) |
| D1LN_RX_WA_SYNC_PAT1_L | 36 (0b00100100) |
| D1LN_RX_WA_SYNC_PAT2_EN | 1 (0b1) |
| D1LN_RX_WA_SYNC_PAT2_H | 25 (0b0011001) |
| D1LN_RX_WA_SYNC_PAT2_L | 36 (0b00100100) |
| D1LN_RX_WA_SYNC_PAT3_EN | 0 (0b0) |
| D1LN_RX_WA_SYNC_PAT3_H | 9 (0b0001001) |
| D1LN_RX_WA_SYNC_PAT3_L | 36 (0b00100100) |
| D1LN_RX_W_LENDIAN | 1 (0b1) |
| D1LN_TX_REASGN_A | 0 (0b00) |
| D1LN_TX_REASGN_B | 1 (0b01) |
| D1LN_TX_REASGN_C | 2 (0b10) |
| D2LN_HS_RX_EN | 1 (0b1) |
| D2LN_HS_TX_EN | 1 (0b1) |
| D2LN_RX_HS_21BIT_MODE | 0 (0b0) |
| D2LN_RX_REASGN_A | 0 (0b00) |
| D2LN_RX_REASGN_B | 1 (0b01) |
| D2LN_RX_REASGN_C | 2 (0b10) |
| D2LN_RX_WA_SYNC_PAT0_EN | 1 (0b1) |
| D2LN_RX_WA_SYNC_PAT0_H | 73 (0b1001001) |
| D2LN_RX_WA_SYNC_PAT0_L | 36 (0b00100100) |
| D2LN_RX_WA_SYNC_PAT1_EN | 1 (0b1) |
| D2LN_RX_WA_SYNC_PAT1_H | 41 (0b0101001) |
| D2LN_RX_WA_SYNC_PAT1_L | 36 (0b00100100) |
| D2LN_RX_WA_SYNC_PAT2_EN | 1 (0b1) |
| D2LN_RX_WA_SYNC_PAT2_H | 25 (0b0011001) |
| D2LN_RX_WA_SYNC_PAT2_L | 36 (0b00100100) |
| D2LN_RX_WA_SYNC_PAT3_EN | 0 (0b0) |
| D2LN_RX_WA_SYNC_PAT3_H | 9 (0b0001001) |
| D2LN_RX_WA_SYNC_PAT3_L | 36 (0b00100100) |
| D2LN_RX_W_LENDIAN | 1 (0b1) |
| D2LN_TX_REASGN_A | 0 (0b00) |
| D2LN_TX_REASGN_B | 1 (0b01) |
| D2LN_TX_REASGN_C | 2 (0b10) |
| EQ_CS_LN0 | 5 (0b101) |
| EQ_CS_LN1 | 5 (0b101) |
| EQ_CS_LN2 | 5 (0b101) |
| EQ_PBIAS_LN0 | 4 (0b0100) |
| EQ_PBIAS_LN1 | 4 (0b0100) |
| EQ_PBIAS_LN2 | 4 (0b0100) |
| EQ_RS_LN0 | 1 (0b001) |
| EQ_RS_LN1 | 1 (0b001) |
| EQ_RS_LN2 | 1 (0b001) |
| EQ_ZLD_LN0 | 8 (0b1000) |
| EQ_ZLD_LN1 | 8 (0b1000) |
| EQ_ZLD_LN2 | 8 (0b1000) |
| HSRX_LNSEL | 7 (0b111) |
| LNDIV_EN | 0 (0b0) |
| LNDIV_RATIO | 0 (0b0000) |
| PGA_BIAS_LN0 | 8 (0b1000) |
| PGA_BIAS_LN1 | 8 (0b1000) |
| PGA_BIAS_LN2 | 8 (0b1000) |
| PGA_GAIN_LN0 | 6 (0b0110) |
| PGA_GAIN_LN1 | 6 (0b0110) |
| PGA_GAIN_LN2 | 6 (0b0110) |
| RX_OUTCLK_SEL | 0 (0b00) |
| TX_HS_21BIT_MODE | 0 (0b0) |
| TX_PLLCLK | NONE |
| TX_W_LENDIAN | 1 (0b1) |
MIPI_CPHY #(
.CLK_SEL(CLK_SEL),
.D0LN_HS_RX_EN(D0LN_HS_RX_EN),
.D0LN_HS_TX_EN(D0LN_HS_TX_EN),
.D0LN_RX_HS_21BIT_MODE(D0LN_RX_HS_21BIT_MODE),
.D0LN_RX_REASGN_A(D0LN_RX_REASGN_A),
.D0LN_RX_REASGN_B(D0LN_RX_REASGN_B),
.D0LN_RX_REASGN_C(D0LN_RX_REASGN_C),
.D0LN_RX_WA_SYNC_PAT0_EN(D0LN_RX_WA_SYNC_PAT0_EN),
.D0LN_RX_WA_SYNC_PAT0_H(D0LN_RX_WA_SYNC_PAT0_H),
.D0LN_RX_WA_SYNC_PAT0_L(D0LN_RX_WA_SYNC_PAT0_L),
.D0LN_RX_WA_SYNC_PAT1_EN(D0LN_RX_WA_SYNC_PAT1_EN),
.D0LN_RX_WA_SYNC_PAT1_H(D0LN_RX_WA_SYNC_PAT1_H),
.D0LN_RX_WA_SYNC_PAT1_L(D0LN_RX_WA_SYNC_PAT1_L),
.D0LN_RX_WA_SYNC_PAT2_EN(D0LN_RX_WA_SYNC_PAT2_EN),
.D0LN_RX_WA_SYNC_PAT2_H(D0LN_RX_WA_SYNC_PAT2_H),
.D0LN_RX_WA_SYNC_PAT2_L(D0LN_RX_WA_SYNC_PAT2_L),
.D0LN_RX_WA_SYNC_PAT3_EN(D0LN_RX_WA_SYNC_PAT3_EN),
.D0LN_RX_WA_SYNC_PAT3_H(D0LN_RX_WA_SYNC_PAT3_H),
.D0LN_RX_WA_SYNC_PAT3_L(D0LN_RX_WA_SYNC_PAT3_L),
.D0LN_RX_W_LENDIAN(D0LN_RX_W_LENDIAN),
.D0LN_TX_REASGN_A(D0LN_TX_REASGN_A),
.D0LN_TX_REASGN_B(D0LN_TX_REASGN_B),
.D0LN_TX_REASGN_C(D0LN_TX_REASGN_C),
.D1LN_HS_RX_EN(D1LN_HS_RX_EN),
.D1LN_HS_TX_EN(D1LN_HS_TX_EN),
.D1LN_RX_HS_21BIT_MODE(D1LN_RX_HS_21BIT_MODE),
.D1LN_RX_REASGN_A(D1LN_RX_REASGN_A),
.D1LN_RX_REASGN_B(D1LN_RX_REASGN_B),
.D1LN_RX_REASGN_C(D1LN_RX_REASGN_C),
.D1LN_RX_WA_SYNC_PAT0_EN(D1LN_RX_WA_SYNC_PAT0_EN),
.D1LN_RX_WA_SYNC_PAT0_H(D1LN_RX_WA_SYNC_PAT0_H),
.D1LN_RX_WA_SYNC_PAT0_L(D1LN_RX_WA_SYNC_PAT0_L),
.D1LN_RX_WA_SYNC_PAT1_EN(D1LN_RX_WA_SYNC_PAT1_EN),
.D1LN_RX_WA_SYNC_PAT1_H(D1LN_RX_WA_SYNC_PAT1_H),
.D1LN_RX_WA_SYNC_PAT1_L(D1LN_RX_WA_SYNC_PAT1_L),
.D1LN_RX_WA_SYNC_PAT2_EN(D1LN_RX_WA_SYNC_PAT2_EN),
.D1LN_RX_WA_SYNC_PAT2_H(D1LN_RX_WA_SYNC_PAT2_H),
.D1LN_RX_WA_SYNC_PAT2_L(D1LN_RX_WA_SYNC_PAT2_L),
.D1LN_RX_WA_SYNC_PAT3_EN(D1LN_RX_WA_SYNC_PAT3_EN),
.D1LN_RX_WA_SYNC_PAT3_H(D1LN_RX_WA_SYNC_PAT3_H),
.D1LN_RX_WA_SYNC_PAT3_L(D1LN_RX_WA_SYNC_PAT3_L),
.D1LN_RX_W_LENDIAN(D1LN_RX_W_LENDIAN),
.D1LN_TX_REASGN_A(D1LN_TX_REASGN_A),
.D1LN_TX_REASGN_B(D1LN_TX_REASGN_B),
.D1LN_TX_REASGN_C(D1LN_TX_REASGN_C),
.D2LN_HS_RX_EN(D2LN_HS_RX_EN),
.D2LN_HS_TX_EN(D2LN_HS_TX_EN),
.D2LN_RX_HS_21BIT_MODE(D2LN_RX_HS_21BIT_MODE),
.D2LN_RX_REASGN_A(D2LN_RX_REASGN_A),
.D2LN_RX_REASGN_B(D2LN_RX_REASGN_B),
.D2LN_RX_REASGN_C(D2LN_RX_REASGN_C),
.D2LN_RX_WA_SYNC_PAT0_EN(D2LN_RX_WA_SYNC_PAT0_EN),
.D2LN_RX_WA_SYNC_PAT0_H(D2LN_RX_WA_SYNC_PAT0_H),
.D2LN_RX_WA_SYNC_PAT0_L(D2LN_RX_WA_SYNC_PAT0_L),
.D2LN_RX_WA_SYNC_PAT1_EN(D2LN_RX_WA_SYNC_PAT1_EN),
.D2LN_RX_WA_SYNC_PAT1_H(D2LN_RX_WA_SYNC_PAT1_H),
.D2LN_RX_WA_SYNC_PAT1_L(D2LN_RX_WA_SYNC_PAT1_L),
.D2LN_RX_WA_SYNC_PAT2_EN(D2LN_RX_WA_SYNC_PAT2_EN),
.D2LN_RX_WA_SYNC_PAT2_H(D2LN_RX_WA_SYNC_PAT2_H),
.D2LN_RX_WA_SYNC_PAT2_L(D2LN_RX_WA_SYNC_PAT2_L),
.D2LN_RX_WA_SYNC_PAT3_EN(D2LN_RX_WA_SYNC_PAT3_EN),
.D2LN_RX_WA_SYNC_PAT3_H(D2LN_RX_WA_SYNC_PAT3_H),
.D2LN_RX_WA_SYNC_PAT3_L(D2LN_RX_WA_SYNC_PAT3_L),
.D2LN_RX_W_LENDIAN(D2LN_RX_W_LENDIAN),
.D2LN_TX_REASGN_A(D2LN_TX_REASGN_A),
.D2LN_TX_REASGN_B(D2LN_TX_REASGN_B),
.D2LN_TX_REASGN_C(D2LN_TX_REASGN_C),
.EQ_CS_LN0(EQ_CS_LN0),
.EQ_CS_LN1(EQ_CS_LN1),
.EQ_CS_LN2(EQ_CS_LN2),
.EQ_PBIAS_LN0(EQ_PBIAS_LN0),
.EQ_PBIAS_LN1(EQ_PBIAS_LN1),
.EQ_PBIAS_LN2(EQ_PBIAS_LN2),
.EQ_RS_LN0(EQ_RS_LN0),
.EQ_RS_LN1(EQ_RS_LN1),
.EQ_RS_LN2(EQ_RS_LN2),
.EQ_ZLD_LN0(EQ_ZLD_LN0),
.EQ_ZLD_LN1(EQ_ZLD_LN1),
.EQ_ZLD_LN2(EQ_ZLD_LN2),
.HSRX_LNSEL(HSRX_LNSEL),
.LNDIV_EN(LNDIV_EN),
.LNDIV_RATIO(LNDIV_RATIO),
.PGA_BIAS_LN0(PGA_BIAS_LN0),
.PGA_BIAS_LN1(PGA_BIAS_LN1),
.PGA_BIAS_LN2(PGA_BIAS_LN2),
.PGA_GAIN_LN0(PGA_GAIN_LN0),
.PGA_GAIN_LN1(PGA_GAIN_LN1),
.PGA_GAIN_LN2(PGA_GAIN_LN2),
.RX_OUTCLK_SEL(RX_OUTCLK_SEL),
.TX_HS_21BIT_MODE(TX_HS_21BIT_MODE),
.TX_PLLCLK(TX_PLLCLK),
.TX_W_LENDIAN(TX_W_LENDIAN)
) mipi_cphy_inst (
.ARSTN_TX(ARSTN_TX),
.ARST_RXLN0(ARST_RXLN0),
.ARST_RXLN1(ARST_RXLN1),
.ARST_RXLN2(ARST_RXLN2),
.D0A(D0A),
.D0B(D0B),
.D0C(D0C),
.D0LN_HSRXD(D0LN_HSRXD),
.D0LN_HSRXD_VLD(D0LN_HSRXD_VLD),
.D0LN_HSRX_DEMAP_INVLD(D0LN_HSRX_DEMAP_INVLD),
.D0LN_HSRX_EN(D0LN_HSRX_EN),
.D0LN_HSRX_FIFO_RDE_ERR(D0LN_HSRX_FIFO_RDE_ERR),
.D0LN_HSRX_FIFO_WRF_ERR(D0LN_HSRX_FIFO_WRF_ERR),
.D0LN_HSRX_WA(D0LN_HSRX_WA),
.D0LN_HSTX_DATA(D0LN_HSTX_DATA),
.D0LN_HSTX_DATA_VLD(D0LN_HSTX_DATA_VLD),
.D0LN_HSTX_EN(D0LN_HSTX_EN),
.D0LN_HSTX_MAP_DIS(D0LN_HSTX_MAP_DIS),
.D0LN_RX_CLK_1X_I(D0LN_RX_CLK_1X_I),
.D0LN_RX_CLK_1X_O(D0LN_RX_CLK_1X_O),
.D0LN_RX_DRST_N(D0LN_RX_DRST_N),
.D0LN_TX_DRST_N(D0LN_TX_DRST_N),
.D1A(D1A),
.D1B(D1B),
.D1C(D1C),
.D1LN_HSRXD(D1LN_HSRXD),
.D1LN_HSRXD_VLD(D1LN_HSRXD_VLD),
.D1LN_HSRX_DEMAP_INVLD(D1LN_HSRX_DEMAP_INVLD),
.D1LN_HSRX_EN(D1LN_HSRX_EN),
.D1LN_HSRX_FIFO_RDE_ERR(D1LN_HSRX_FIFO_RDE_ERR),
.D1LN_HSRX_FIFO_WRF_ERR(D1LN_HSRX_FIFO_WRF_ERR),
.D1LN_HSRX_WA(D1LN_HSRX_WA),
.D1LN_HSTX_DATA(D1LN_HSTX_DATA),
.D1LN_HSTX_DATA_VLD(D1LN_HSTX_DATA_VLD),
.D1LN_HSTX_EN(D1LN_HSTX_EN),
.D1LN_HSTX_MAP_DIS(D1LN_HSTX_MAP_DIS),
.D1LN_RX_CLK_1X_I(D1LN_RX_CLK_1X_I),
.D1LN_RX_CLK_1X_O(D1LN_RX_CLK_1X_O),
.D1LN_RX_DRST_N(D1LN_RX_DRST_N),
.D1LN_TX_DRST_N(D1LN_TX_DRST_N),
.D2A(D2A),
.D2B(D2B),
.D2C(D2C),
.D2LN_HSRXD(D2LN_HSRXD),
.D2LN_HSRXD_VLD(D2LN_HSRXD_VLD),
.D2LN_HSRX_DEMAP_INVLD(D2LN_HSRX_DEMAP_INVLD),
.D2LN_HSRX_EN(D2LN_HSRX_EN),
.D2LN_HSRX_FIFO_RDE_ERR(D2LN_HSRX_FIFO_RDE_ERR),
.D2LN_HSRX_FIFO_WRF_ERR(D2LN_HSRX_FIFO_WRF_ERR),
.D2LN_HSRX_WA(D2LN_HSRX_WA),
.D2LN_HSTX_DATA(D2LN_HSTX_DATA),
.D2LN_HSTX_DATA_VLD(D2LN_HSTX_DATA_VLD),
.D2LN_HSTX_EN(D2LN_HSTX_EN),
.D2LN_HSTX_MAP_DIS(D2LN_HSTX_MAP_DIS),
.D2LN_RX_CLK_1X_I(D2LN_RX_CLK_1X_I),
.D2LN_RX_CLK_1X_O(D2LN_RX_CLK_1X_O),
.D2LN_RX_DRST_N(D2LN_RX_DRST_N),
.D2LN_TX_DRST_N(D2LN_TX_DRST_N),
.DI_LPRX0_A(DI_LPRX0_A),
.DI_LPRX0_B(DI_LPRX0_B),
.DI_LPRX0_C(DI_LPRX0_C),
.DI_LPRX1_A(DI_LPRX1_A),
.DI_LPRX1_B(DI_LPRX1_B),
.DI_LPRX1_C(DI_LPRX1_C),
.DI_LPRX2_A(DI_LPRX2_A),
.DI_LPRX2_B(DI_LPRX2_B),
.DI_LPRX2_C(DI_LPRX2_C),
.DO_LPTX_A_LN0(DO_LPTX_A_LN0),
.DO_LPTX_A_LN1(DO_LPTX_A_LN1),
.DO_LPTX_A_LN2(DO_LPTX_A_LN2),
.DO_LPTX_B_LN0(DO_LPTX_B_LN0),
.DO_LPTX_B_LN1(DO_LPTX_B_LN1),
.DO_LPTX_B_LN2(DO_LPTX_B_LN2),
.DO_LPTX_C_LN0(DO_LPTX_C_LN0),
.DO_LPTX_C_LN1(DO_LPTX_C_LN1),
.DO_LPTX_C_LN2(DO_LPTX_C_LN2),
.GPLL_CK0(GPLL_CK0),
.GPLL_CK180(GPLL_CK180),
.GPLL_CK270(GPLL_CK270),
.GPLL_CK90(GPLL_CK90),
.HSRX_EN_D0(HSRX_EN_D0),
.HSRX_EN_D1(HSRX_EN_D1),
.HSRX_EN_D2(HSRX_EN_D2),
.HSRX_ODT_EN_D0(HSRX_ODT_EN_D0),
.HSRX_ODT_EN_D1(HSRX_ODT_EN_D1),
.HSRX_ODT_EN_D2(HSRX_ODT_EN_D2),
.HSTX_ENLN0(HSTX_ENLN0),
.HSTX_ENLN1(HSTX_ENLN1),
.HSTX_ENLN2(HSTX_ENLN2),
.HSTX_FIFO_AE(HSTX_FIFO_AE),
.HSTX_FIFO_AF(HSTX_FIFO_AF),
.HSTX_FIFO_RDE_ERR(HSTX_FIFO_RDE_ERR),
.HSTX_FIFO_WRF_ERR(HSTX_FIFO_WRF_ERR),
.LPRX_EN_D0(LPRX_EN_D0),
.LPRX_EN_D1(LPRX_EN_D1),
.LPRX_EN_D2(LPRX_EN_D2),
.LPTX_ENLN0(LPTX_ENLN0),
.LPTX_ENLN1(LPTX_ENLN1),
.LPTX_ENLN2(LPTX_ENLN2),
.MDRP_A_D_I(MDRP_A_D_I),
.MDRP_A_INC_I(MDRP_A_INC_I),
.MDRP_CLK_I(MDRP_CLK_I),
.MDRP_OPCODE_I(MDRP_OPCODE_I),
.MDRP_RDATA(MDRP_RDATA),
.PWRON_RX_LN0(PWRON_RX_LN0),
.PWRON_RX_LN1(PWRON_RX_LN1),
.PWRON_RX_LN2(PWRON_RX_LN2),
.PWRON_TX(PWRON_TX),
.RX_CLK_EN_LN0(RX_CLK_EN_LN0),
.RX_CLK_EN_LN1(RX_CLK_EN_LN1),
.RX_CLK_EN_LN2(RX_CLK_EN_LN2),
.RX_CLK_MUXED(RX_CLK_MUXED),
.SPLL0_CKN(SPLL0_CKN),
.SPLL0_CKP(SPLL0_CKP),
.SPLL1_CKN(SPLL1_CKN),
.SPLL1_CKP(SPLL1_CKP),
.TXDP_ENLN0(TXDP_ENLN0),
.TXDP_ENLN1(TXDP_ENLN1),
.TXDP_ENLN2(TXDP_ENLN2),
.TXHCLK_EN(TXHCLK_EN),
.TX_CLK_1X_I(TX_CLK_1X_I),
.TX_CLK_1X_O(TX_CLK_1X_O)
);The MIPI_CPHY_IBUF primitive supports both LP (Low Power) mode and HS (High Speed) mode. In LP mode, it allows for bidirectional functionality when OEN is low, and switching between input and output based on the states of OEN, OENB, OL0/OL1/OL2, and OB0/OB1/OB2. In HS mode, IO0, IOB0, IO1, IOB1, IO2, and IOB2 are differential inputs with outputs OH0, OH1, and OH2 controlled by HSEN.
This device is not yet supported in Apicula
| Port | Size | Direction |
|---|---|---|
| HSEN | 1 | input |
| I0 | 1 | input |
| I1 | 1 | input |
| I2 | 1 | input |
| IB0 | 1 | input |
| IB1 | 1 | input |
| IB2 | 1 | input |
| IO0 | 1 | inout |
| IO1 | 1 | inout |
| IO2 | 1 | inout |
| IOB0 | 1 | inout |
| IOB1 | 1 | inout |
| IOB2 | 1 | inout |
| OB0 | 1 | output |
| OB1 | 1 | output |
| OB2 | 1 | output |
| OEN | 1 | input |
| OENB | 1 | input |
| OH0 | 1 | output |
| OH1 | 1 | output |
| OH2 | 1 | output |
| OL0 | 1 | output |
| OL1 | 1 | output |
| OL2 | 1 | output |
MIPI_CPHY_IBUF mipi_cphy_ibuf_inst (
.HSEN(HSEN),
.I0(I0),
.I1(I1),
.I2(I2),
.IB0(IB0),
.IB1(IB1),
.IB2(IB2),
.IO0(IO0),
.IO1(IO1),
.IO2(IO2),
.IOB0(IOB0),
.IOB1(IOB1),
.IOB2(IOB2),
.OB0(OB0),
.OB1(OB1),
.OB2(OB2),
.OEN(OEN),
.OENB(OENB),
.OH0(OH0),
.OH1(OH1),
.OH2(OH2),
.OL0(OL0),
.OL1(OL1),
.OL2(OL2)
);The MIPI_CPHY_OBUF primitive includes HS (high-speed) and LP (low-power) modes. In HS mode, when MODESEL is high, it acts as a MIPI CPHY output buffer with three pairs of I/Os: (I0, O0), (I1, O1), and (I2, O2). When MODESEL is low, it acts as an LP MIPI CPHY bi-directional buffer.
This device is not yet supported in Apicula
| Port | Size | Direction |
|---|---|---|
| I0 | 1 | input |
| I1 | 1 | input |
| I2 | 1 | input |
| IB0 | 1 | input |
| IB1 | 1 | input |
| IB2 | 1 | input |
| IL0 | 1 | input |
| IL1 | 1 | input |
| IL2 | 1 | input |
| IO0 | 1 | inout |
| IO1 | 1 | inout |
| IO2 | 1 | inout |
| IOB0 | 1 | inout |
| IOB1 | 1 | inout |
| IOB2 | 1 | inout |
| MODESEL | 1 | input |
| O0 | 1 | output |
| O1 | 1 | output |
| O2 | 1 | output |
| OB0 | 1 | output |
| OB1 | 1 | output |
| OB2 | 1 | output |
| OEN | 1 | input |
| OENB | 1 | input |
| VCOME | 1 | input |
MIPI_CPHY_OBUF mipi_cphy_obuf_inst (
.I0(I0),
.I1(I1),
.I2(I2),
.IB0(IB0),
.IB1(IB1),
.IB2(IB2),
.IL0(IL0),
.IL1(IL1),
.IL2(IL2),
.IO0(IO0),
.IO1(IO1),
.IO2(IO2),
.IOB0(IOB0),
.IOB1(IOB1),
.IOB2(IOB2),
.MODESEL(MODESEL),
.O0(O0),
.O1(O1),
.O2(O2),
.OB0(OB0),
.OB1(OB1),
.OB2(OB2),
.OEN(OEN),
.OENB(OENB),
.VCOME(VCOME)
);This device is not yet supported in Apicula
| Port | Size | Direction |
|---|---|---|
| ALPEDO_LANE0 | 1 | output |
| ALPEDO_LANE1 | 1 | output |
| ALPEDO_LANE2 | 1 | output |
| ALPEDO_LANE3 | 1 | output |
| ALPEDO_LANECK | 1 | output |
| ALPEN_LN0 | 1 | input |
| ALPEN_LN1 | 1 | input |
| ALPEN_LN2 | 1 | input |
| ALPEN_LN3 | 1 | input |
| ALPEN_LNCK | 1 | input |
| ALP_EDEN_LANE0 | 1 | input |
| ALP_EDEN_LANE1 | 1 | input |
| ALP_EDEN_LANE2 | 1 | input |
| ALP_EDEN_LANE3 | 1 | input |
| ALP_EDEN_LANECK | 1 | input |
| CK0 | 1 | input |
| CK180 | 1 | input |
| CK270 | 1 | input |
| CK90 | 1 | input |
| CKLN_HSTXD | 16 | input |
| CK_N | 1 | inout |
| CK_P | 1 | inout |
| D0LN_DESKEW_DONE | 1 | output |
| D0LN_DESKEW_ERROR | 1 | output |
| D0LN_DESKEW_REQ | 1 | input |
| D0LN_HSRXD | 16 | output |
| D0LN_HSRXD_VLD | 1 | output |
| D0LN_HSRX_DREN | 1 | input |
| D0LN_HSTXD | 16 | input |
| D0_N | 1 | inout |
| D0_P | 1 | inout |
| D1LN_DESKEW_DONE | 1 | output |
| D1LN_DESKEW_ERROR | 1 | output |
| D1LN_DESKEW_REQ | 1 | input |
| D1LN_HSRXD | 16 | output |
| D1LN_HSRXD_VLD | 1 | output |
| D1LN_HSRX_DREN | 1 | input |
| D1LN_HSTXD | 16 | input |
| D1_N | 1 | inout |
| D1_P | 1 | inout |
| D2LN_DESKEW_DONE | 1 | output |
| D2LN_DESKEW_ERROR | 1 | output |
| D2LN_DESKEW_REQ | 1 | input |
| D2LN_HSRXD | 16 | output |
| D2LN_HSRXD_VLD | 1 | output |
| D2LN_HSRX_DREN | 1 | input |
| D2LN_HSTXD | 16 | input |
| D2_N | 1 | inout |
| D2_P | 1 | inout |
| D3LN_DESKEW_DONE | 1 | output |
| D3LN_DESKEW_ERROR | 1 | output |
| D3LN_DESKEW_REQ | 1 | input |
| D3LN_HSRXD | 16 | output |
| D3LN_HSRXD_VLD | 1 | output |
| D3LN_HSRX_DREN | 1 | input |
| D3LN_HSTXD | 16 | input |
| D3_N | 1 | inout |
| D3_P | 1 | inout |
| DI_LPRX0_N | 1 | output |
| DI_LPRX0_P | 1 | output |
| DI_LPRX1_N | 1 | output |
| DI_LPRX1_P | 1 | output |
| DI_LPRX2_N | 1 | output |
| DI_LPRX2_P | 1 | output |
| DI_LPRX3_N | 1 | output |
| DI_LPRX3_P | 1 | output |
| DI_LPRXCK_N | 1 | output |
| DI_LPRXCK_P | 1 | output |
| DO_LPTX0_N | 1 | input |
| DO_LPTX0_P | 1 | input |
| DO_LPTX1_N | 1 | input |
| DO_LPTX1_P | 1 | input |
| DO_LPTX2_N | 1 | input |
| DO_LPTX2_P | 1 | input |
| DO_LPTX3_N | 1 | input |
| DO_LPTX3_P | 1 | input |
| DO_LPTXCK_N | 1 | input |
| DO_LPTXCK_P | 1 | input |
| HSRX_DLYDIR_LANE0 | 1 | input |
| HSRX_DLYDIR_LANE1 | 1 | input |
| HSRX_DLYDIR_LANE2 | 1 | input |
| HSRX_DLYDIR_LANE3 | 1 | input |
| HSRX_DLYDIR_LANECK | 1 | input |
| HSRX_DLYLDN_LANE0 | 1 | input |
| HSRX_DLYLDN_LANE1 | 1 | input |
| HSRX_DLYLDN_LANE2 | 1 | input |
| HSRX_DLYLDN_LANE3 | 1 | input |
| HSRX_DLYLDN_LANECK | 1 | input |
| HSRX_DLYMV_LANE0 | 1 | input |
| HSRX_DLYMV_LANE1 | 1 | input |
| HSRX_DLYMV_LANE2 | 1 | input |
| HSRX_DLYMV_LANE3 | 1 | input |
| HSRX_DLYMV_LANECK | 1 | input |
| HSRX_EN_CK | 1 | input |
| HSRX_EN_D0 | 1 | input |
| HSRX_EN_D1 | 1 | input |
| HSRX_EN_D2 | 1 | input |
| HSRX_EN_D3 | 1 | input |
| HSRX_ODTEN_CK | 1 | input |
| HSRX_STOP | 1 | input |
| HSTXD_VLD | 1 | input |
| HSTXEN_LN0 | 1 | input |
| HSTXEN_LN1 | 1 | input |
| HSTXEN_LN2 | 1 | input |
| HSTXEN_LN3 | 1 | input |
| HSTXEN_LNCK | 1 | input |
| MA_INC | 1 | input |
| MCLK | 1 | input |
| MOPCODE | 2 | input |
| MRDATA | 8 | output |
| MWDATA | 8 | input |
| PWRON_RX | 1 | input |
| PWRON_TX | 1 | input |
| RESET | 1 | input |
| RX_CLK_1X | 1 | input |
| RX_CLK_O | 1 | output |
| RX_DRST_N | 1 | input |
| TXDPEN_LN0 | 1 | input |
| TXDPEN_LN1 | 1 | input |
| TXDPEN_LN2 | 1 | input |
| TXDPEN_LN3 | 1 | input |
| TXDPEN_LNCK | 1 | input |
| TXHCLK_EN | 1 | input |
| TX_CLK_1X | 1 | input |
| TX_CLK_O | 1 | output |
| TX_DRST_N | 1 | input |
| WALIGN_DVLD | 1 | input |
| Parameter | Default Value |
|---|---|
| ALP_ED_EN_LANE0 | 1 (0b1) |
| ALP_ED_EN_LANE1 | 1 (0b1) |
| ALP_ED_EN_LANE2 | 1 (0b1) |
| ALP_ED_EN_LANE3 | 1 (0b1) |
| ALP_ED_EN_LANECK | 1 (0b1) |
| ALP_ED_TST_LANE0 | 0 (0b0) |
| ALP_ED_TST_LANE1 | 0 (0b0) |
| ALP_ED_TST_LANE2 | 0 (0b0) |
| ALP_ED_TST_LANE3 | 0 (0b0) |
| ALP_ED_TST_LANECK | 0 (0b0) |
| ALP_EN_LN0 | 0 (0b0) |
| ALP_EN_LN1 | 0 (0b0) |
| ALP_EN_LN2 | 0 (0b0) |
| ALP_EN_LN3 | 0 (0b0) |
| ALP_EN_LNCK | 0 (0b0) |
| ALP_HYS_EN_LANE0 | 1 (0b1) |
| ALP_HYS_EN_LANE1 | 1 (0b1) |
| ALP_HYS_EN_LANE2 | 1 (0b1) |
| ALP_HYS_EN_LANE3 | 1 (0b1) |
| ALP_HYS_EN_LANECK | 1 (0b1) |
| ALP_TH_LANE0 | 8 (0b1000) |
| ALP_TH_LANE1 | 8 (0b1000) |
| ALP_TH_LANE2 | 8 (0b1000) |
| ALP_TH_LANE3 | 8 (0b1000) |
| ALP_TH_LANECK | 8 (0b1000) |
| ANA_BYTECLK_PH | 0 (0b00) |
| BIT_REVERSE_LN0 | 0 (0b0) |
| BIT_REVERSE_LN1 | 0 (0b0) |
| BIT_REVERSE_LN2 | 0 (0b0) |
| BIT_REVERSE_LN3 | 0 (0b0) |
| BIT_REVERSE_LNCK | 0 (0b0) |
| BYPASS_TXHCLKEN | 1 (0b1) |
| BYPASS_TXHCLKEN_SYNC | 0 (0b0) |
| BYTE_CLK_POLAR | 0 (0b0) |
| BYTE_REVERSE_LN0 | 0 (0b0) |
| BYTE_REVERSE_LN1 | 0 (0b0) |
| BYTE_REVERSE_LN2 | 0 (0b0) |
| BYTE_REVERSE_LN3 | 0 (0b0) |
| BYTE_REVERSE_LNCK | 0 (0b0) |
| CKLN_DELAY_EN | 0 (0b0) |
| CKLN_DELAY_OVR_VAL | 0 (0b0000000) |
| D0LN_DELAY_EN | 0 (0b0) |
| D0LN_DELAY_OVR_VAL | 0 (0b0000000) |
| D0LN_DESKEW_BYPASS | 0 (0b0) |
| D1LN_DELAY_EN | 0 (0b0) |
| D1LN_DELAY_OVR_VAL | 0 (0b0000000) |
| D1LN_DESKEW_BYPASS | 0 (0b0) |
| D2LN_DELAY_EN | 0 (0b0) |
| D2LN_DELAY_OVR_VAL | 0 (0b0000000) |
| D2LN_DESKEW_BYPASS | 0 (0b0) |
| D3LN_DELAY_EN | 0 (0b0) |
| D3LN_DELAY_OVR_VAL | 0 (0b0000000) |
| D3LN_DESKEW_BYPASS | 0 (0b0) |
| DESKEW_EN_LOW_DELAY | 0 (0b0) |
| DESKEW_EN_ONE_EDGE | 0 (0b0) |
| DESKEW_FAST_LOOP_TIME | 0 (0b0000) |
| DESKEW_FAST_MODE | 0 (0b0) |
| DESKEW_HALF_OPENING | 22 (0b010110) |
| DESKEW_LSB_MODE | 0 (0b00) |
| DESKEW_M | 3 (0b011) |
| DESKEW_MAX_SETTING | 33 (0b0100001) |
| DESKEW_M_TH | 422 (0b0000110100110) |
| DESKEW_ONE_CLK_EDGE_EN | 0 (0b0) |
| DESKEW_RST_BYPASS | 0 (0b0) |
| EN_CLKB1X | 1 (0b1) |
| EQ_CS_LANE0 | 4 (0b100) |
| EQ_CS_LANE1 | 4 (0b100) |
| EQ_CS_LANE2 | 4 (0b100) |
| EQ_CS_LANE3 | 4 (0b100) |
| EQ_CS_LANECK | 4 (0b100) |
| EQ_PBIAS_LANE0 | 8 (0b1000) |
| EQ_PBIAS_LANE1 | 8 (0b1000) |
| EQ_PBIAS_LANE2 | 8 (0b1000) |
| EQ_PBIAS_LANE3 | 8 (0b1000) |
| EQ_PBIAS_LANECK | 8 (0b1000) |
| EQ_RS_LANE0 | 4 (0b100) |
| EQ_RS_LANE1 | 4 (0b100) |
| EQ_RS_LANE2 | 4 (0b100) |
| EQ_RS_LANE3 | 4 (0b100) |
| EQ_RS_LANECK | 4 (0b100) |
| EQ_ZLD_LANE0 | 8 (0b1000) |
| EQ_ZLD_LANE1 | 8 (0b1000) |
| EQ_ZLD_LANE2 | 8 (0b1000) |
| EQ_ZLD_LANE3 | 8 (0b1000) |
| EQ_ZLD_LANECK | 8 (0b1000) |
| HIGH_BW_LANE0 | 1 (0b1) |
| HIGH_BW_LANE1 | 1 (0b1) |
| HIGH_BW_LANE2 | 1 (0b1) |
| HIGH_BW_LANE3 | 1 (0b1) |
| HIGH_BW_LANECK | 1 (0b1) |
| HSCLK_LANE_LN0 | 0 (0b0) |
| HSCLK_LANE_LN1 | 0 (0b0) |
| HSCLK_LANE_LN2 | 0 (0b0) |
| HSCLK_LANE_LN3 | 0 (0b0) |
| HSCLK_LANE_LNCK | 1 (0b1) |
| HSREG_EN_LN0 | 0 (0b0) |
| HSREG_EN_LN1 | 0 (0b0) |
| HSREG_EN_LN2 | 0 (0b0) |
| HSREG_EN_LN3 | 0 (0b0) |
| HSREG_EN_LNCK | 0 (0b0) |
| HSREG_VREF_CTL | 4 (0b100) |
| HSREG_VREF_EN | 1 (0b1) |
| HSRX_DLY_CTL_CK | 0 (0b0000000) |
| HSRX_DLY_CTL_LANE0 | 0 (0b0000000) |
| HSRX_DLY_CTL_LANE1 | 0 (0b0000000) |
| HSRX_DLY_CTL_LANE2 | 0 (0b0000000) |
| HSRX_DLY_CTL_LANE3 | 0 (0b0000000) |
| HSRX_DLY_SEL_LANE0 | 0 (0b0) |
| HSRX_DLY_SEL_LANE1 | 0 (0b0) |
| HSRX_DLY_SEL_LANE2 | 0 (0b0) |
| HSRX_DLY_SEL_LANE3 | 0 (0b0) |
| HSRX_DLY_SEL_LANECK | 0 (0b0) |
| HSRX_DUTY_LANE0 | 8 (0b1000) |
| HSRX_DUTY_LANE1 | 8 (0b1000) |
| HSRX_DUTY_LANE2 | 8 (0b1000) |
| HSRX_DUTY_LANE3 | 8 (0b1000) |
| HSRX_DUTY_LANECK | 8 (0b1000) |
| HSRX_EN | 1 (0b1) |
| HSRX_EQ_EN_LANE0 | 1 (0b1) |
| HSRX_EQ_EN_LANE1 | 1 (0b1) |
| HSRX_EQ_EN_LANE2 | 1 (0b1) |
| HSRX_EQ_EN_LANE3 | 1 (0b1) |
| HSRX_EQ_EN_LANECK | 1 (0b1) |
| HSRX_IBIAS | 3 (0b0011) |
| HSRX_IBIAS_TEST_EN | 0 (0b0) |
| HSRX_IMARG_EN | 0 (0b0) |
| HSRX_LANESEL | 15 (0b1111) |
| HSRX_LANESEL_CK | 1 (0b1) |
| HSRX_ODT_EN | 1 (0b1) |
| HSRX_ODT_TST | 0 (0b0000) |
| HSRX_ODT_TST_CK | 0 (0b0) |
| HSRX_SEL | 0 (0b0000) |
| HSRX_STOP_EN | 0 (0b0) |
| HSRX_TST | 0 (0b0000) |
| HSRX_TST_CK | 0 (0b0) |
| HSRX_WAIT4EDGE | 1 (0b1) |
| HSTX_EN_LN0 | 0 (0b0) |
| HSTX_EN_LN1 | 0 (0b0) |
| HSTX_EN_LN2 | 0 (0b0) |
| HSTX_EN_LN3 | 0 (0b0) |
| HSTX_EN_LNCK | 0 (0b0) |
| HYST_NCTL | 1 (0b01) |
| HYST_PCTL | 1 (0b01) |
| IBIAS_TEST_EN | 0 (0b0) |
| LANE_DIV_SEL | 0 (0b00) |
| LB_CH_SEL | 0 (0b0) |
| LB_EN_LN0 | 0 (0b0) |
| LB_EN_LN1 | 0 (0b0) |
| LB_EN_LN2 | 0 (0b0) |
| LB_EN_LN3 | 0 (0b0) |
| LB_EN_LNCK | 0 (0b0) |
| LB_POLAR_LN0 | 0 (0b0) |
| LB_POLAR_LN1 | 0 (0b0) |
| LB_POLAR_LN2 | 0 (0b0) |
| LB_POLAR_LN3 | 0 (0b0) |
| LB_POLAR_LNCK | 0 (0b0) |
| LOW_LPRX_VTH | 0 (0b0) |
| LPBKTST_EN | 0 (0b0000) |
| LPBKTST_EN_CK | 0 (0b0) |
| LPBK_DATA2TO1 | 0 (0b0000) |
| LPBK_DATA2TO1_CK | 0 (0b0) |
| LPBK_EN | 0 (0b0) |
| LPBK_SEL | 0 (0b0000) |
| LPRX_EN | 1 (0b1) |
| LPRX_TST | 0 (0b0000) |
| LPRX_TST_CK | 0 (0b0) |
| LPTX_DAT_POLAR_LN0 | 0 (0b0) |
| LPTX_DAT_POLAR_LN1 | 0 (0b0) |
| LPTX_DAT_POLAR_LN2 | 0 (0b0) |
| LPTX_DAT_POLAR_LN3 | 0 (0b0) |
| LPTX_DAT_POLAR_LNCK | 0 (0b0) |
| LPTX_EN_LN0 | 1 (0b1) |
| LPTX_EN_LN1 | 1 (0b1) |
| LPTX_EN_LN2 | 1 (0b1) |
| LPTX_EN_LN3 | 1 (0b1) |
| LPTX_EN_LNCK | 1 (0b1) |
| LPTX_NIMP_LN0 | 4 (0b100) |
| LPTX_NIMP_LN1 | 4 (0b100) |
| LPTX_NIMP_LN2 | 4 (0b100) |
| LPTX_NIMP_LN3 | 4 (0b100) |
| LPTX_NIMP_LNCK | 4 (0b100) |
| LPTX_PIMP_LN0 | 4 (0b100) |
| LPTX_PIMP_LN1 | 4 (0b100) |
| LPTX_PIMP_LN2 | 4 (0b100) |
| LPTX_PIMP_LN3 | 4 (0b100) |
| LPTX_PIMP_LNCK | 4 (0b100) |
| MIPI_PMA_DIS_N | 1 (0b1) |
| PGA_BIAS_LANE0 | 8 (0b1000) |
| PGA_BIAS_LANE1 | 8 (0b1000) |
| PGA_BIAS_LANE2 | 8 (0b1000) |
| PGA_BIAS_LANE3 | 8 (0b1000) |
| PGA_BIAS_LANECK | 8 (0b1000) |
| PGA_GAIN_LANE0 | 8 (0b1000) |
| PGA_GAIN_LANE1 | 8 (0b1000) |
| PGA_GAIN_LANE2 | 8 (0b1000) |
| PGA_GAIN_LANE3 | 8 (0b1000) |
| PGA_GAIN_LANECK | 8 (0b1000) |
| RX_ALIGN_BYTE | 184 (0b10111000) |
| RX_BYTE_LITTLE_ENDIAN | 1 (0b1) |
| RX_CLK_1X_SYNC_SEL | 0 (0b0) |
| RX_HS_8BIT_MODE | 0 (0b0) |
| RX_INVERT | 0 (0b0) |
| RX_LANE_ALIGN_EN | 0 (0b0) |
| RX_ODT_TRIM_LANE0 | 8 (0b1000) |
| RX_ODT_TRIM_LANE1 | 8 (0b1000) |
| RX_ODT_TRIM_LANE2 | 8 (0b1000) |
| RX_ODT_TRIM_LANE3 | 8 (0b1000) |
| RX_ODT_TRIM_LANECK | 8 (0b1000) |
| RX_ONE_BYTE0_MATCH | 0 (0b0) |
| RX_RD_START_DEPTH | 1 (0b00001) |
| RX_SYNC_MODE | 0 (0b0) |
| RX_WORD_ALIGN_BYPASS | 0 (0b0) |
| RX_WORD_ALIGN_DATA_VLD_SRC_SEL | 0 (0b0) |
| RX_WORD_LITTLE_ENDIAN | 1 (0b1) |
| SLEWN_CTL_LN0 | 15 (0b1111) |
| SLEWN_CTL_LN1 | 15 (0b1111) |
| SLEWN_CTL_LN2 | 15 (0b1111) |
| SLEWN_CTL_LN3 | 15 (0b1111) |
| SLEWN_CTL_LNCK | 15 (0b1111) |
| SLEWP_CTL_LN0 | 15 (0b1111) |
| SLEWP_CTL_LN1 | 15 (0b1111) |
| SLEWP_CTL_LN2 | 15 (0b1111) |
| SLEWP_CTL_LN3 | 15 (0b1111) |
| SLEWP_CTL_LNCK | 15 (0b1111) |
| STP_UNIT | 1 (0b01) |
| TERMN_CTL_LN0 | 8 (0b1000) |
| TERMN_CTL_LN1 | 8 (0b1000) |
| TERMN_CTL_LN2 | 8 (0b1000) |
| TERMN_CTL_LN3 | 8 (0b1000) |
| TERMN_CTL_LNCK | 8 (0b1000) |
| TERMP_CTL_LN0 | 8 (0b1000) |
| TERMP_CTL_LN1 | 8 (0b1000) |
| TERMP_CTL_LN2 | 8 (0b1000) |
| TERMP_CTL_LN3 | 8 (0b1000) |
| TERMP_CTL_LNCK | 8 (0b1000) |
| TEST_EN_LN0 | 0 (0b0) |
| TEST_EN_LN1 | 0 (0b0) |
| TEST_EN_LN2 | 0 (0b0) |
| TEST_EN_LN3 | 0 (0b0) |
| TEST_EN_LNCK | 0 (0b0) |
| TEST_N_IMP_LN0 | 0 (0b0) |
| TEST_N_IMP_LN1 | 0 (0b0) |
| TEST_N_IMP_LN2 | 0 (0b0) |
| TEST_N_IMP_LN3 | 0 (0b0) |
| TEST_N_IMP_LNCK | 0 (0b0) |
| TEST_P_IMP_LN0 | 0 (0b0) |
| TEST_P_IMP_LN1 | 0 (0b0) |
| TEST_P_IMP_LN2 | 0 (0b0) |
| TEST_P_IMP_LN3 | 0 (0b0) |
| TEST_P_IMP_LNCK | 0 (0b0) |
| TXDP_EN_LN0 | 0 (0b0) |
| TXDP_EN_LN1 | 0 (0b0) |
| TXDP_EN_LN2 | 0 (0b0) |
| TXDP_EN_LN3 | 0 (0b0) |
| TXDP_EN_LNCK | 0 (0b0) |
| TX_BYPASS_MODE | 0 (0b0) |
| TX_BYTECLK_SYNC_MODE | 0 (0b0) |
| TX_HS_8BIT_MODE | 0 (0b0) |
| TX_OCLK_USE_CIBCLK | 0 (0b0) |
| TX_PLLCLK | NONE |
| TX_RD_START_DEPTH | 1 (0b00001) |
| TX_SYNC_MODE | 0 (0b0) |
| TX_WORD_LITTLE_ENDIAN | 1 (0b1) |
MIPI_DPHY #(
.ALP_ED_EN_LANE0(ALP_ED_EN_LANE0),
.ALP_ED_EN_LANE1(ALP_ED_EN_LANE1),
.ALP_ED_EN_LANE2(ALP_ED_EN_LANE2),
.ALP_ED_EN_LANE3(ALP_ED_EN_LANE3),
.ALP_ED_EN_LANECK(ALP_ED_EN_LANECK),
.ALP_ED_TST_LANE0(ALP_ED_TST_LANE0),
.ALP_ED_TST_LANE1(ALP_ED_TST_LANE1),
.ALP_ED_TST_LANE2(ALP_ED_TST_LANE2),
.ALP_ED_TST_LANE3(ALP_ED_TST_LANE3),
.ALP_ED_TST_LANECK(ALP_ED_TST_LANECK),
.ALP_EN_LN0(ALP_EN_LN0),
.ALP_EN_LN1(ALP_EN_LN1),
.ALP_EN_LN2(ALP_EN_LN2),
.ALP_EN_LN3(ALP_EN_LN3),
.ALP_EN_LNCK(ALP_EN_LNCK),
.ALP_HYS_EN_LANE0(ALP_HYS_EN_LANE0),
.ALP_HYS_EN_LANE1(ALP_HYS_EN_LANE1),
.ALP_HYS_EN_LANE2(ALP_HYS_EN_LANE2),
.ALP_HYS_EN_LANE3(ALP_HYS_EN_LANE3),
.ALP_HYS_EN_LANECK(ALP_HYS_EN_LANECK),
.ALP_TH_LANE0(ALP_TH_LANE0),
.ALP_TH_LANE1(ALP_TH_LANE1),
.ALP_TH_LANE2(ALP_TH_LANE2),
.ALP_TH_LANE3(ALP_TH_LANE3),
.ALP_TH_LANECK(ALP_TH_LANECK),
.ANA_BYTECLK_PH(ANA_BYTECLK_PH),
.BIT_REVERSE_LN0(BIT_REVERSE_LN0),
.BIT_REVERSE_LN1(BIT_REVERSE_LN1),
.BIT_REVERSE_LN2(BIT_REVERSE_LN2),
.BIT_REVERSE_LN3(BIT_REVERSE_LN3),
.BIT_REVERSE_LNCK(BIT_REVERSE_LNCK),
.BYPASS_TXHCLKEN(BYPASS_TXHCLKEN),
.BYPASS_TXHCLKEN_SYNC(BYPASS_TXHCLKEN_SYNC),
.BYTE_CLK_POLAR(BYTE_CLK_POLAR),
.BYTE_REVERSE_LN0(BYTE_REVERSE_LN0),
.BYTE_REVERSE_LN1(BYTE_REVERSE_LN1),
.BYTE_REVERSE_LN2(BYTE_REVERSE_LN2),
.BYTE_REVERSE_LN3(BYTE_REVERSE_LN3),
.BYTE_REVERSE_LNCK(BYTE_REVERSE_LNCK),
.CKLN_DELAY_EN(CKLN_DELAY_EN),
.CKLN_DELAY_OVR_VAL(CKLN_DELAY_OVR_VAL),
.D0LN_DELAY_EN(D0LN_DELAY_EN),
.D0LN_DELAY_OVR_VAL(D0LN_DELAY_OVR_VAL),
.D0LN_DESKEW_BYPASS(D0LN_DESKEW_BYPASS),
.D1LN_DELAY_EN(D1LN_DELAY_EN),
.D1LN_DELAY_OVR_VAL(D1LN_DELAY_OVR_VAL),
.D1LN_DESKEW_BYPASS(D1LN_DESKEW_BYPASS),
.D2LN_DELAY_EN(D2LN_DELAY_EN),
.D2LN_DELAY_OVR_VAL(D2LN_DELAY_OVR_VAL),
.D2LN_DESKEW_BYPASS(D2LN_DESKEW_BYPASS),
.D3LN_DELAY_EN(D3LN_DELAY_EN),
.D3LN_DELAY_OVR_VAL(D3LN_DELAY_OVR_VAL),
.D3LN_DESKEW_BYPASS(D3LN_DESKEW_BYPASS),
.DESKEW_EN_LOW_DELAY(DESKEW_EN_LOW_DELAY),
.DESKEW_EN_ONE_EDGE(DESKEW_EN_ONE_EDGE),
.DESKEW_FAST_LOOP_TIME(DESKEW_FAST_LOOP_TIME),
.DESKEW_FAST_MODE(DESKEW_FAST_MODE),
.DESKEW_HALF_OPENING(DESKEW_HALF_OPENING),
.DESKEW_LSB_MODE(DESKEW_LSB_MODE),
.DESKEW_M(DESKEW_M),
.DESKEW_MAX_SETTING(DESKEW_MAX_SETTING),
.DESKEW_M_TH(DESKEW_M_TH),
.DESKEW_ONE_CLK_EDGE_EN(DESKEW_ONE_CLK_EDGE_EN),
.DESKEW_RST_BYPASS(DESKEW_RST_BYPASS),
.EN_CLKB1X(EN_CLKB1X),
.EQ_CS_LANE0(EQ_CS_LANE0),
.EQ_CS_LANE1(EQ_CS_LANE1),
.EQ_CS_LANE2(EQ_CS_LANE2),
.EQ_CS_LANE3(EQ_CS_LANE3),
.EQ_CS_LANECK(EQ_CS_LANECK),
.EQ_PBIAS_LANE0(EQ_PBIAS_LANE0),
.EQ_PBIAS_LANE1(EQ_PBIAS_LANE1),
.EQ_PBIAS_LANE2(EQ_PBIAS_LANE2),
.EQ_PBIAS_LANE3(EQ_PBIAS_LANE3),
.EQ_PBIAS_LANECK(EQ_PBIAS_LANECK),
.EQ_RS_LANE0(EQ_RS_LANE0),
.EQ_RS_LANE1(EQ_RS_LANE1),
.EQ_RS_LANE2(EQ_RS_LANE2),
.EQ_RS_LANE3(EQ_RS_LANE3),
.EQ_RS_LANECK(EQ_RS_LANECK),
.EQ_ZLD_LANE0(EQ_ZLD_LANE0),
.EQ_ZLD_LANE1(EQ_ZLD_LANE1),
.EQ_ZLD_LANE2(EQ_ZLD_LANE2),
.EQ_ZLD_LANE3(EQ_ZLD_LANE3),
.EQ_ZLD_LANECK(EQ_ZLD_LANECK),
.HIGH_BW_LANE0(HIGH_BW_LANE0),
.HIGH_BW_LANE1(HIGH_BW_LANE1),
.HIGH_BW_LANE2(HIGH_BW_LANE2),
.HIGH_BW_LANE3(HIGH_BW_LANE3),
.HIGH_BW_LANECK(HIGH_BW_LANECK),
.HSCLK_LANE_LN0(HSCLK_LANE_LN0),
.HSCLK_LANE_LN1(HSCLK_LANE_LN1),
.HSCLK_LANE_LN2(HSCLK_LANE_LN2),
.HSCLK_LANE_LN3(HSCLK_LANE_LN3),
.HSCLK_LANE_LNCK(HSCLK_LANE_LNCK),
.HSREG_EN_LN0(HSREG_EN_LN0),
.HSREG_EN_LN1(HSREG_EN_LN1),
.HSREG_EN_LN2(HSREG_EN_LN2),
.HSREG_EN_LN3(HSREG_EN_LN3),
.HSREG_EN_LNCK(HSREG_EN_LNCK),
.HSREG_VREF_CTL(HSREG_VREF_CTL),
.HSREG_VREF_EN(HSREG_VREF_EN),
.HSRX_DLY_CTL_CK(HSRX_DLY_CTL_CK),
.HSRX_DLY_CTL_LANE0(HSRX_DLY_CTL_LANE0),
.HSRX_DLY_CTL_LANE1(HSRX_DLY_CTL_LANE1),
.HSRX_DLY_CTL_LANE2(HSRX_DLY_CTL_LANE2),
.HSRX_DLY_CTL_LANE3(HSRX_DLY_CTL_LANE3),
.HSRX_DLY_SEL_LANE0(HSRX_DLY_SEL_LANE0),
.HSRX_DLY_SEL_LANE1(HSRX_DLY_SEL_LANE1),
.HSRX_DLY_SEL_LANE2(HSRX_DLY_SEL_LANE2),
.HSRX_DLY_SEL_LANE3(HSRX_DLY_SEL_LANE3),
.HSRX_DLY_SEL_LANECK(HSRX_DLY_SEL_LANECK),
.HSRX_DUTY_LANE0(HSRX_DUTY_LANE0),
.HSRX_DUTY_LANE1(HSRX_DUTY_LANE1),
.HSRX_DUTY_LANE2(HSRX_DUTY_LANE2),
.HSRX_DUTY_LANE3(HSRX_DUTY_LANE3),
.HSRX_DUTY_LANECK(HSRX_DUTY_LANECK),
.HSRX_EN(HSRX_EN),
.HSRX_EQ_EN_LANE0(HSRX_EQ_EN_LANE0),
.HSRX_EQ_EN_LANE1(HSRX_EQ_EN_LANE1),
.HSRX_EQ_EN_LANE2(HSRX_EQ_EN_LANE2),
.HSRX_EQ_EN_LANE3(HSRX_EQ_EN_LANE3),
.HSRX_EQ_EN_LANECK(HSRX_EQ_EN_LANECK),
.HSRX_IBIAS(HSRX_IBIAS),
.HSRX_IBIAS_TEST_EN(HSRX_IBIAS_TEST_EN),
.HSRX_IMARG_EN(HSRX_IMARG_EN),
.HSRX_LANESEL(HSRX_LANESEL),
.HSRX_LANESEL_CK(HSRX_LANESEL_CK),
.HSRX_ODT_EN(HSRX_ODT_EN),
.HSRX_ODT_TST(HSRX_ODT_TST),
.HSRX_ODT_TST_CK(HSRX_ODT_TST_CK),
.HSRX_SEL(HSRX_SEL),
.HSRX_STOP_EN(HSRX_STOP_EN),
.HSRX_TST(HSRX_TST),
.HSRX_TST_CK(HSRX_TST_CK),
.HSRX_WAIT4EDGE(HSRX_WAIT4EDGE),
.HSTX_EN_LN0(HSTX_EN_LN0),
.HSTX_EN_LN1(HSTX_EN_LN1),
.HSTX_EN_LN2(HSTX_EN_LN2),
.HSTX_EN_LN3(HSTX_EN_LN3),
.HSTX_EN_LNCK(HSTX_EN_LNCK),
.HYST_NCTL(HYST_NCTL),
.HYST_PCTL(HYST_PCTL),
.IBIAS_TEST_EN(IBIAS_TEST_EN),
.LANE_DIV_SEL(LANE_DIV_SEL),
.LB_CH_SEL(LB_CH_SEL),
.LB_EN_LN0(LB_EN_LN0),
.LB_EN_LN1(LB_EN_LN1),
.LB_EN_LN2(LB_EN_LN2),
.LB_EN_LN3(LB_EN_LN3),
.LB_EN_LNCK(LB_EN_LNCK),
.LB_POLAR_LN0(LB_POLAR_LN0),
.LB_POLAR_LN1(LB_POLAR_LN1),
.LB_POLAR_LN2(LB_POLAR_LN2),
.LB_POLAR_LN3(LB_POLAR_LN3),
.LB_POLAR_LNCK(LB_POLAR_LNCK),
.LOW_LPRX_VTH(LOW_LPRX_VTH),
.LPBKTST_EN(LPBKTST_EN),
.LPBKTST_EN_CK(LPBKTST_EN_CK),
.LPBK_DATA2TO1(LPBK_DATA2TO1),
.LPBK_DATA2TO1_CK(LPBK_DATA2TO1_CK),
.LPBK_EN(LPBK_EN),
.LPBK_SEL(LPBK_SEL),
.LPRX_EN(LPRX_EN),
.LPRX_TST(LPRX_TST),
.LPRX_TST_CK(LPRX_TST_CK),
.LPTX_DAT_POLAR_LN0(LPTX_DAT_POLAR_LN0),
.LPTX_DAT_POLAR_LN1(LPTX_DAT_POLAR_LN1),
.LPTX_DAT_POLAR_LN2(LPTX_DAT_POLAR_LN2),
.LPTX_DAT_POLAR_LN3(LPTX_DAT_POLAR_LN3),
.LPTX_DAT_POLAR_LNCK(LPTX_DAT_POLAR_LNCK),
.LPTX_EN_LN0(LPTX_EN_LN0),
.LPTX_EN_LN1(LPTX_EN_LN1),
.LPTX_EN_LN2(LPTX_EN_LN2),
.LPTX_EN_LN3(LPTX_EN_LN3),
.LPTX_EN_LNCK(LPTX_EN_LNCK),
.LPTX_NIMP_LN0(LPTX_NIMP_LN0),
.LPTX_NIMP_LN1(LPTX_NIMP_LN1),
.LPTX_NIMP_LN2(LPTX_NIMP_LN2),
.LPTX_NIMP_LN3(LPTX_NIMP_LN3),
.LPTX_NIMP_LNCK(LPTX_NIMP_LNCK),
.LPTX_PIMP_LN0(LPTX_PIMP_LN0),
.LPTX_PIMP_LN1(LPTX_PIMP_LN1),
.LPTX_PIMP_LN2(LPTX_PIMP_LN2),
.LPTX_PIMP_LN3(LPTX_PIMP_LN3),
.LPTX_PIMP_LNCK(LPTX_PIMP_LNCK),
.MIPI_PMA_DIS_N(MIPI_PMA_DIS_N),
.PGA_BIAS_LANE0(PGA_BIAS_LANE0),
.PGA_BIAS_LANE1(PGA_BIAS_LANE1),
.PGA_BIAS_LANE2(PGA_BIAS_LANE2),
.PGA_BIAS_LANE3(PGA_BIAS_LANE3),
.PGA_BIAS_LANECK(PGA_BIAS_LANECK),
.PGA_GAIN_LANE0(PGA_GAIN_LANE0),
.PGA_GAIN_LANE1(PGA_GAIN_LANE1),
.PGA_GAIN_LANE2(PGA_GAIN_LANE2),
.PGA_GAIN_LANE3(PGA_GAIN_LANE3),
.PGA_GAIN_LANECK(PGA_GAIN_LANECK),
.RX_ALIGN_BYTE(RX_ALIGN_BYTE),
.RX_BYTE_LITTLE_ENDIAN(RX_BYTE_LITTLE_ENDIAN),
.RX_CLK_1X_SYNC_SEL(RX_CLK_1X_SYNC_SEL),
.RX_HS_8BIT_MODE(RX_HS_8BIT_MODE),
.RX_INVERT(RX_INVERT),
.RX_LANE_ALIGN_EN(RX_LANE_ALIGN_EN),
.RX_ODT_TRIM_LANE0(RX_ODT_TRIM_LANE0),
.RX_ODT_TRIM_LANE1(RX_ODT_TRIM_LANE1),
.RX_ODT_TRIM_LANE2(RX_ODT_TRIM_LANE2),
.RX_ODT_TRIM_LANE3(RX_ODT_TRIM_LANE3),
.RX_ODT_TRIM_LANECK(RX_ODT_TRIM_LANECK),
.RX_ONE_BYTE0_MATCH(RX_ONE_BYTE0_MATCH),
.RX_RD_START_DEPTH(RX_RD_START_DEPTH),
.RX_SYNC_MODE(RX_SYNC_MODE),
.RX_WORD_ALIGN_BYPASS(RX_WORD_ALIGN_BYPASS),
.RX_WORD_ALIGN_DATA_VLD_SRC_SEL(RX_WORD_ALIGN_DATA_VLD_SRC_SEL),
.RX_WORD_LITTLE_ENDIAN(RX_WORD_LITTLE_ENDIAN),
.SLEWN_CTL_LN0(SLEWN_CTL_LN0),
.SLEWN_CTL_LN1(SLEWN_CTL_LN1),
.SLEWN_CTL_LN2(SLEWN_CTL_LN2),
.SLEWN_CTL_LN3(SLEWN_CTL_LN3),
.SLEWN_CTL_LNCK(SLEWN_CTL_LNCK),
.SLEWP_CTL_LN0(SLEWP_CTL_LN0),
.SLEWP_CTL_LN1(SLEWP_CTL_LN1),
.SLEWP_CTL_LN2(SLEWP_CTL_LN2),
.SLEWP_CTL_LN3(SLEWP_CTL_LN3),
.SLEWP_CTL_LNCK(SLEWP_CTL_LNCK),
.STP_UNIT(STP_UNIT),
.TERMN_CTL_LN0(TERMN_CTL_LN0),
.TERMN_CTL_LN1(TERMN_CTL_LN1),
.TERMN_CTL_LN2(TERMN_CTL_LN2),
.TERMN_CTL_LN3(TERMN_CTL_LN3),
.TERMN_CTL_LNCK(TERMN_CTL_LNCK),
.TERMP_CTL_LN0(TERMP_CTL_LN0),
.TERMP_CTL_LN1(TERMP_CTL_LN1),
.TERMP_CTL_LN2(TERMP_CTL_LN2),
.TERMP_CTL_LN3(TERMP_CTL_LN3),
.TERMP_CTL_LNCK(TERMP_CTL_LNCK),
.TEST_EN_LN0(TEST_EN_LN0),
.TEST_EN_LN1(TEST_EN_LN1),
.TEST_EN_LN2(TEST_EN_LN2),
.TEST_EN_LN3(TEST_EN_LN3),
.TEST_EN_LNCK(TEST_EN_LNCK),
.TEST_N_IMP_LN0(TEST_N_IMP_LN0),
.TEST_N_IMP_LN1(TEST_N_IMP_LN1),
.TEST_N_IMP_LN2(TEST_N_IMP_LN2),
.TEST_N_IMP_LN3(TEST_N_IMP_LN3),
.TEST_N_IMP_LNCK(TEST_N_IMP_LNCK),
.TEST_P_IMP_LN0(TEST_P_IMP_LN0),
.TEST_P_IMP_LN1(TEST_P_IMP_LN1),
.TEST_P_IMP_LN2(TEST_P_IMP_LN2),
.TEST_P_IMP_LN3(TEST_P_IMP_LN3),
.TEST_P_IMP_LNCK(TEST_P_IMP_LNCK),
.TXDP_EN_LN0(TXDP_EN_LN0),
.TXDP_EN_LN1(TXDP_EN_LN1),
.TXDP_EN_LN2(TXDP_EN_LN2),
.TXDP_EN_LN3(TXDP_EN_LN3),
.TXDP_EN_LNCK(TXDP_EN_LNCK),
.TX_BYPASS_MODE(TX_BYPASS_MODE),
.TX_BYTECLK_SYNC_MODE(TX_BYTECLK_SYNC_MODE),
.TX_HS_8BIT_MODE(TX_HS_8BIT_MODE),
.TX_OCLK_USE_CIBCLK(TX_OCLK_USE_CIBCLK),
.TX_PLLCLK(TX_PLLCLK),
.TX_RD_START_DEPTH(TX_RD_START_DEPTH),
.TX_SYNC_MODE(TX_SYNC_MODE),
.TX_WORD_LITTLE_ENDIAN(TX_WORD_LITTLE_ENDIAN)
) mipi_dphy_inst (
.ALPEDO_LANE0(ALPEDO_LANE0),
.ALPEDO_LANE1(ALPEDO_LANE1),
.ALPEDO_LANE2(ALPEDO_LANE2),
.ALPEDO_LANE3(ALPEDO_LANE3),
.ALPEDO_LANECK(ALPEDO_LANECK),
.ALPEN_LN0(ALPEN_LN0),
.ALPEN_LN1(ALPEN_LN1),
.ALPEN_LN2(ALPEN_LN2),
.ALPEN_LN3(ALPEN_LN3),
.ALPEN_LNCK(ALPEN_LNCK),
.ALP_EDEN_LANE0(ALP_EDEN_LANE0),
.ALP_EDEN_LANE1(ALP_EDEN_LANE1),
.ALP_EDEN_LANE2(ALP_EDEN_LANE2),
.ALP_EDEN_LANE3(ALP_EDEN_LANE3),
.ALP_EDEN_LANECK(ALP_EDEN_LANECK),
.CK0(CK0),
.CK180(CK180),
.CK270(CK270),
.CK90(CK90),
.CKLN_HSTXD(CKLN_HSTXD),
.CK_N(CK_N),
.CK_P(CK_P),
.D0LN_DESKEW_DONE(D0LN_DESKEW_DONE),
.D0LN_DESKEW_ERROR(D0LN_DESKEW_ERROR),
.D0LN_DESKEW_REQ(D0LN_DESKEW_REQ),
.D0LN_HSRXD(D0LN_HSRXD),
.D0LN_HSRXD_VLD(D0LN_HSRXD_VLD),
.D0LN_HSRX_DREN(D0LN_HSRX_DREN),
.D0LN_HSTXD(D0LN_HSTXD),
.D0_N(D0_N),
.D0_P(D0_P),
.D1LN_DESKEW_DONE(D1LN_DESKEW_DONE),
.D1LN_DESKEW_ERROR(D1LN_DESKEW_ERROR),
.D1LN_DESKEW_REQ(D1LN_DESKEW_REQ),
.D1LN_HSRXD(D1LN_HSRXD),
.D1LN_HSRXD_VLD(D1LN_HSRXD_VLD),
.D1LN_HSRX_DREN(D1LN_HSRX_DREN),
.D1LN_HSTXD(D1LN_HSTXD),
.D1_N(D1_N),
.D1_P(D1_P),
.D2LN_DESKEW_DONE(D2LN_DESKEW_DONE),
.D2LN_DESKEW_ERROR(D2LN_DESKEW_ERROR),
.D2LN_DESKEW_REQ(D2LN_DESKEW_REQ),
.D2LN_HSRXD(D2LN_HSRXD),
.D2LN_HSRXD_VLD(D2LN_HSRXD_VLD),
.D2LN_HSRX_DREN(D2LN_HSRX_DREN),
.D2LN_HSTXD(D2LN_HSTXD),
.D2_N(D2_N),
.D2_P(D2_P),
.D3LN_DESKEW_DONE(D3LN_DESKEW_DONE),
.D3LN_DESKEW_ERROR(D3LN_DESKEW_ERROR),
.D3LN_DESKEW_REQ(D3LN_DESKEW_REQ),
.D3LN_HSRXD(D3LN_HSRXD),
.D3LN_HSRXD_VLD(D3LN_HSRXD_VLD),
.D3LN_HSRX_DREN(D3LN_HSRX_DREN),
.D3LN_HSTXD(D3LN_HSTXD),
.D3_N(D3_N),
.D3_P(D3_P),
.DI_LPRX0_N(DI_LPRX0_N),
.DI_LPRX0_P(DI_LPRX0_P),
.DI_LPRX1_N(DI_LPRX1_N),
.DI_LPRX1_P(DI_LPRX1_P),
.DI_LPRX2_N(DI_LPRX2_N),
.DI_LPRX2_P(DI_LPRX2_P),
.DI_LPRX3_N(DI_LPRX3_N),
.DI_LPRX3_P(DI_LPRX3_P),
.DI_LPRXCK_N(DI_LPRXCK_N),
.DI_LPRXCK_P(DI_LPRXCK_P),
.DO_LPTX0_N(DO_LPTX0_N),
.DO_LPTX0_P(DO_LPTX0_P),
.DO_LPTX1_N(DO_LPTX1_N),
.DO_LPTX1_P(DO_LPTX1_P),
.DO_LPTX2_N(DO_LPTX2_N),
.DO_LPTX2_P(DO_LPTX2_P),
.DO_LPTX3_N(DO_LPTX3_N),
.DO_LPTX3_P(DO_LPTX3_P),
.DO_LPTXCK_N(DO_LPTXCK_N),
.DO_LPTXCK_P(DO_LPTXCK_P),
.HSRX_DLYDIR_LANE0(HSRX_DLYDIR_LANE0),
.HSRX_DLYDIR_LANE1(HSRX_DLYDIR_LANE1),
.HSRX_DLYDIR_LANE2(HSRX_DLYDIR_LANE2),
.HSRX_DLYDIR_LANE3(HSRX_DLYDIR_LANE3),
.HSRX_DLYDIR_LANECK(HSRX_DLYDIR_LANECK),
.HSRX_DLYLDN_LANE0(HSRX_DLYLDN_LANE0),
.HSRX_DLYLDN_LANE1(HSRX_DLYLDN_LANE1),
.HSRX_DLYLDN_LANE2(HSRX_DLYLDN_LANE2),
.HSRX_DLYLDN_LANE3(HSRX_DLYLDN_LANE3),
.HSRX_DLYLDN_LANECK(HSRX_DLYLDN_LANECK),
.HSRX_DLYMV_LANE0(HSRX_DLYMV_LANE0),
.HSRX_DLYMV_LANE1(HSRX_DLYMV_LANE1),
.HSRX_DLYMV_LANE2(HSRX_DLYMV_LANE2),
.HSRX_DLYMV_LANE3(HSRX_DLYMV_LANE3),
.HSRX_DLYMV_LANECK(HSRX_DLYMV_LANECK),
.HSRX_EN_CK(HSRX_EN_CK),
.HSRX_EN_D0(HSRX_EN_D0),
.HSRX_EN_D1(HSRX_EN_D1),
.HSRX_EN_D2(HSRX_EN_D2),
.HSRX_EN_D3(HSRX_EN_D3),
.HSRX_ODTEN_CK(HSRX_ODTEN_CK),
.HSRX_STOP(HSRX_STOP),
.HSTXD_VLD(HSTXD_VLD),
.HSTXEN_LN0(HSTXEN_LN0),
.HSTXEN_LN1(HSTXEN_LN1),
.HSTXEN_LN2(HSTXEN_LN2),
.HSTXEN_LN3(HSTXEN_LN3),
.HSTXEN_LNCK(HSTXEN_LNCK),
.MA_INC(MA_INC),
.MCLK(MCLK),
.MOPCODE(MOPCODE),
.MRDATA(MRDATA),
.MWDATA(MWDATA),
.PWRON_RX(PWRON_RX),
.PWRON_TX(PWRON_TX),
.RESET(RESET),
.RX_CLK_1X(RX_CLK_1X),
.RX_CLK_O(RX_CLK_O),
.RX_DRST_N(RX_DRST_N),
.TXDPEN_LN0(TXDPEN_LN0),
.TXDPEN_LN1(TXDPEN_LN1),
.TXDPEN_LN2(TXDPEN_LN2),
.TXDPEN_LN3(TXDPEN_LN3),
.TXDPEN_LNCK(TXDPEN_LNCK),
.TXHCLK_EN(TXHCLK_EN),
.TX_CLK_1X(TX_CLK_1X),
.TX_CLK_O(TX_CLK_O),
.TX_DRST_N(TX_DRST_N),
.WALIGN_DVLD(WALIGN_DVLD)
);This device is not yet supported in Apicula
| Port | Size | Direction |
|---|---|---|
| ALPEDO_LANE0 | 1 | output |
| ALPEDO_LANE1 | 1 | output |
| ALPEDO_LANE2 | 1 | output |
| ALPEDO_LANE3 | 1 | output |
| ALPEDO_LANECK | 1 | output |
| ALPEN_LN0 | 1 | input |
| ALPEN_LN1 | 1 | input |
| ALPEN_LN2 | 1 | input |
| ALPEN_LN3 | 1 | input |
| ALPEN_LNCK | 1 | input |
| ALP_EDEN_LANE0 | 1 | input |
| ALP_EDEN_LANE1 | 1 | input |
| ALP_EDEN_LANE2 | 1 | input |
| ALP_EDEN_LANE3 | 1 | input |
| ALP_EDEN_LANECK | 1 | input |
| CK0 | 1 | input |
| CK180 | 1 | input |
| CK270 | 1 | input |
| CK90 | 1 | input |
| CKLN_HSTXD | 16 | input |
| CK_N | 1 | inout |
| CK_P | 1 | inout |
| D0LN_DESKEW_DONE | 1 | output |
| D0LN_DESKEW_ERROR | 1 | output |
| D0LN_DESKEW_REQ | 1 | input |
| D0LN_HSRXD | 16 | output |
| D0LN_HSRXD_VLD | 1 | output |
| D0LN_HSRX_DREN | 1 | input |
| D0LN_HSTXD | 16 | input |
| D0_N | 1 | inout |
| D0_P | 1 | inout |
| D1LN_DESKEW_DONE | 1 | output |
| D1LN_DESKEW_ERROR | 1 | output |
| D1LN_DESKEW_REQ | 1 | input |
| D1LN_HSRXD | 16 | output |
| D1LN_HSRXD_VLD | 1 | output |
| D1LN_HSRX_DREN | 1 | input |
| D1LN_HSTXD | 16 | input |
| D1_N | 1 | inout |
| D1_P | 1 | inout |
| D2LN_DESKEW_DONE | 1 | output |
| D2LN_DESKEW_ERROR | 1 | output |
| D2LN_DESKEW_REQ | 1 | input |
| D2LN_HSRXD | 16 | output |
| D2LN_HSRXD_VLD | 1 | output |
| D2LN_HSRX_DREN | 1 | input |
| D2LN_HSTXD | 16 | input |
| D2_N | 1 | inout |
| D2_P | 1 | inout |
| D3LN_DESKEW_DONE | 1 | output |
| D3LN_DESKEW_ERROR | 1 | output |
| D3LN_DESKEW_REQ | 1 | input |
| D3LN_HSRXD | 16 | output |
| D3LN_HSRXD_VLD | 1 | output |
| D3LN_HSRX_DREN | 1 | input |
| D3LN_HSTXD | 16 | input |
| D3_N | 1 | inout |
| D3_P | 1 | inout |
| DI_LPRX0_N | 1 | output |
| DI_LPRX0_P | 1 | output |
| DI_LPRX1_N | 1 | output |
| DI_LPRX1_P | 1 | output |
| DI_LPRX2_N | 1 | output |
| DI_LPRX2_P | 1 | output |
| DI_LPRX3_N | 1 | output |
| DI_LPRX3_P | 1 | output |
| DI_LPRXCK_N | 1 | output |
| DI_LPRXCK_P | 1 | output |
| DO_LPTX0_N | 1 | input |
| DO_LPTX0_P | 1 | input |
| DO_LPTX1_N | 1 | input |
| DO_LPTX1_P | 1 | input |
| DO_LPTX2_N | 1 | input |
| DO_LPTX2_P | 1 | input |
| DO_LPTX3_N | 1 | input |
| DO_LPTX3_P | 1 | input |
| DO_LPTXCK_N | 1 | input |
| DO_LPTXCK_P | 1 | input |
| HSRX_DLYDIR_LANE0 | 1 | input |
| HSRX_DLYDIR_LANE1 | 1 | input |
| HSRX_DLYDIR_LANE2 | 1 | input |
| HSRX_DLYDIR_LANE3 | 1 | input |
| HSRX_DLYDIR_LANECK | 1 | input |
| HSRX_DLYLDN_LANE0 | 1 | input |
| HSRX_DLYLDN_LANE1 | 1 | input |
| HSRX_DLYLDN_LANE2 | 1 | input |
| HSRX_DLYLDN_LANE3 | 1 | input |
| HSRX_DLYLDN_LANECK | 1 | input |
| HSRX_DLYMV_LANE0 | 1 | input |
| HSRX_DLYMV_LANE1 | 1 | input |
| HSRX_DLYMV_LANE2 | 1 | input |
| HSRX_DLYMV_LANE3 | 1 | input |
| HSRX_DLYMV_LANECK | 1 | input |
| HSRX_EN_CK | 1 | input |
| HSRX_EN_D0 | 1 | input |
| HSRX_EN_D1 | 1 | input |
| HSRX_EN_D2 | 1 | input |
| HSRX_EN_D3 | 1 | input |
| HSRX_ODTEN_CK | 1 | input |
| HSRX_STOP | 1 | input |
| HSTXD_VLD | 1 | input |
| HSTXEN_LN0 | 1 | input |
| HSTXEN_LN1 | 1 | input |
| HSTXEN_LN2 | 1 | input |
| HSTXEN_LN3 | 1 | input |
| HSTXEN_LNCK | 1 | input |
| MA_INC | 1 | input |
| MCLK | 1 | input |
| MOPCODE | 2 | input |
| MRDATA | 8 | output |
| MWDATA | 8 | input |
| PWRON_RX | 1 | input |
| PWRON_TX | 1 | input |
| RESET | 1 | input |
| RX_CLK_1X | 1 | input |
| RX_CLK_O | 1 | output |
| RX_DRST_N | 1 | input |
| SPLL_CKN | 1 | input |
| SPLL_CKP | 1 | input |
| TXDPEN_LN0 | 1 | input |
| TXDPEN_LN1 | 1 | input |
| TXDPEN_LN2 | 1 | input |
| TXDPEN_LN3 | 1 | input |
| TXDPEN_LNCK | 1 | input |
| TXHCLK_EN | 1 | input |
| TX_CLK_1X | 1 | input |
| TX_CLK_O | 1 | output |
| TX_DRST_N | 1 | input |
| WALIGN_DVLD | 1 | input |
| Parameter | Default Value |
|---|---|
| ALP_ED_EN_LANE0 | 1 (0b1) |
| ALP_ED_EN_LANE1 | 1 (0b1) |
| ALP_ED_EN_LANE2 | 1 (0b1) |
| ALP_ED_EN_LANE3 | 1 (0b1) |
| ALP_ED_EN_LANECK | 1 (0b1) |
| ALP_ED_TST_LANE0 | 0 (0b0) |
| ALP_ED_TST_LANE1 | 0 (0b0) |
| ALP_ED_TST_LANE2 | 0 (0b0) |
| ALP_ED_TST_LANE3 | 0 (0b0) |
| ALP_ED_TST_LANECK | 0 (0b0) |
| ALP_EN_LN0 | 0 (0b0) |
| ALP_EN_LN1 | 0 (0b0) |
| ALP_EN_LN2 | 0 (0b0) |
| ALP_EN_LN3 | 0 (0b0) |
| ALP_EN_LNCK | 0 (0b0) |
| ALP_HYS_EN_LANE0 | 1 (0b1) |
| ALP_HYS_EN_LANE1 | 1 (0b1) |
| ALP_HYS_EN_LANE2 | 1 (0b1) |
| ALP_HYS_EN_LANE3 | 1 (0b1) |
| ALP_HYS_EN_LANECK | 1 (0b1) |
| ALP_TH_LANE0 | 8 (0b1000) |
| ALP_TH_LANE1 | 8 (0b1000) |
| ALP_TH_LANE2 | 8 (0b1000) |
| ALP_TH_LANE3 | 8 (0b1000) |
| ALP_TH_LANECK | 8 (0b1000) |
| ANA_BYTECLK_PH | 0 (0b00) |
| BIT_REVERSE_LN0 | 0 (0b0) |
| BIT_REVERSE_LN1 | 0 (0b0) |
| BIT_REVERSE_LN2 | 0 (0b0) |
| BIT_REVERSE_LN3 | 0 (0b0) |
| BIT_REVERSE_LNCK | 0 (0b0) |
| BYPASS_TXHCLKEN | 1 (0b1) |
| BYPASS_TXHCLKEN_SYNC | 0 (0b0) |
| BYTE_CLK_POLAR | 0 (0b0) |
| BYTE_REVERSE_LN0 | 0 (0b0) |
| BYTE_REVERSE_LN1 | 0 (0b0) |
| BYTE_REVERSE_LN2 | 0 (0b0) |
| BYTE_REVERSE_LN3 | 0 (0b0) |
| BYTE_REVERSE_LNCK | 0 (0b0) |
| CKLN_DELAY_EN | 0 (0b0) |
| CKLN_DELAY_OVR_VAL | 0 (0b0000000) |
| D0LN_DELAY_EN | 0 (0b0) |
| D0LN_DELAY_OVR_VAL | 0 (0b0000000) |
| D0LN_DESKEW_BYPASS | 0 (0b0) |
| D1LN_DELAY_EN | 0 (0b0) |
| D1LN_DELAY_OVR_VAL | 0 (0b0000000) |
| D1LN_DESKEW_BYPASS | 0 (0b0) |
| D2LN_DELAY_EN | 0 (0b0) |
| D2LN_DELAY_OVR_VAL | 0 (0b0000000) |
| D2LN_DESKEW_BYPASS | 0 (0b0) |
| D3LN_DELAY_EN | 0 (0b0) |
| D3LN_DELAY_OVR_VAL | 0 (0b0000000) |
| D3LN_DESKEW_BYPASS | 0 (0b0) |
| DESKEW_EN_LOW_DELAY | 0 (0b0) |
| DESKEW_EN_ONE_EDGE | 0 (0b0) |
| DESKEW_FAST_LOOP_TIME | 0 (0b0000) |
| DESKEW_FAST_MODE | 0 (0b0) |
| DESKEW_HALF_OPENING | 22 (0b010110) |
| DESKEW_LSB_MODE | 0 (0b00) |
| DESKEW_M | 3 (0b011) |
| DESKEW_MAX_SETTING | 33 (0b0100001) |
| DESKEW_M_TH | 422 (0b0000110100110) |
| DESKEW_ONE_CLK_EDGE_EN | 0 (0b0) |
| DESKEW_RST_BYPASS | 0 (0b0) |
| DPHY_CK_SEL | 1 (0b01) |
| EN_CLKB1X | 1 (0b1) |
| EQ_CS_LANE0 | 4 (0b100) |
| EQ_CS_LANE1 | 4 (0b100) |
| EQ_CS_LANE2 | 4 (0b100) |
| EQ_CS_LANE3 | 4 (0b100) |
| EQ_CS_LANECK | 4 (0b100) |
| EQ_PBIAS_LANE0 | 8 (0b1000) |
| EQ_PBIAS_LANE1 | 8 (0b1000) |
| EQ_PBIAS_LANE2 | 8 (0b1000) |
| EQ_PBIAS_LANE3 | 8 (0b1000) |
| EQ_PBIAS_LANECK | 8 (0b1000) |
| EQ_RS_LANE0 | 4 (0b100) |
| EQ_RS_LANE1 | 4 (0b100) |
| EQ_RS_LANE2 | 4 (0b100) |
| EQ_RS_LANE3 | 4 (0b100) |
| EQ_RS_LANECK | 4 (0b100) |
| EQ_ZLD_LANE0 | 8 (0b1000) |
| EQ_ZLD_LANE1 | 8 (0b1000) |
| EQ_ZLD_LANE2 | 8 (0b1000) |
| EQ_ZLD_LANE3 | 8 (0b1000) |
| EQ_ZLD_LANECK | 8 (0b1000) |
| HIGH_BW_LANE0 | 1 (0b1) |
| HIGH_BW_LANE1 | 1 (0b1) |
| HIGH_BW_LANE2 | 1 (0b1) |
| HIGH_BW_LANE3 | 1 (0b1) |
| HIGH_BW_LANECK | 1 (0b1) |
| HSCLK_LANE_LN0 | 0 (0b0) |
| HSCLK_LANE_LN1 | 0 (0b0) |
| HSCLK_LANE_LN2 | 0 (0b0) |
| HSCLK_LANE_LN3 | 0 (0b0) |
| HSCLK_LANE_LNCK | 1 (0b1) |
| HSREG_EN_LN0 | 0 (0b0) |
| HSREG_EN_LN1 | 0 (0b0) |
| HSREG_EN_LN2 | 0 (0b0) |
| HSREG_EN_LN3 | 0 (0b0) |
| HSREG_EN_LNCK | 0 (0b0) |
| HSREG_VREF_CTL | 4 (0b100) |
| HSREG_VREF_EN | 1 (0b1) |
| HSRX_DLY_CTL_CK | 0 (0b0000000) |
| HSRX_DLY_CTL_LANE0 | 0 (0b0000000) |
| HSRX_DLY_CTL_LANE1 | 0 (0b0000000) |
| HSRX_DLY_CTL_LANE2 | 0 (0b0000000) |
| HSRX_DLY_CTL_LANE3 | 0 (0b0000000) |
| HSRX_DLY_SEL_LANE0 | 0 (0b0) |
| HSRX_DLY_SEL_LANE1 | 0 (0b0) |
| HSRX_DLY_SEL_LANE2 | 0 (0b0) |
| HSRX_DLY_SEL_LANE3 | 0 (0b0) |
| HSRX_DLY_SEL_LANECK | 0 (0b0) |
| HSRX_DUTY_LANE0 | 8 (0b1000) |
| HSRX_DUTY_LANE1 | 8 (0b1000) |
| HSRX_DUTY_LANE2 | 8 (0b1000) |
| HSRX_DUTY_LANE3 | 8 (0b1000) |
| HSRX_DUTY_LANECK | 8 (0b1000) |
| HSRX_EN | 1 (0b1) |
| HSRX_EQ_EN_LANE0 | 1 (0b1) |
| HSRX_EQ_EN_LANE1 | 1 (0b1) |
| HSRX_EQ_EN_LANE2 | 1 (0b1) |
| HSRX_EQ_EN_LANE3 | 1 (0b1) |
| HSRX_EQ_EN_LANECK | 1 (0b1) |
| HSRX_IBIAS | 3 (0b0011) |
| HSRX_IBIAS_TEST_EN | 0 (0b0) |
| HSRX_IMARG_EN | 0 (0b0) |
| HSRX_LANESEL | 15 (0b1111) |
| HSRX_LANESEL_CK | 1 (0b1) |
| HSRX_ODT_EN | 1 (0b1) |
| HSRX_ODT_TST | 0 (0b0000) |
| HSRX_ODT_TST_CK | 0 (0b0) |
| HSRX_SEL | 0 (0b0000) |
| HSRX_STOP_EN | 0 (0b0) |
| HSRX_TST | 0 (0b0000) |
| HSRX_TST_CK | 0 (0b0) |
| HSRX_WAIT4EDGE | 1 (0b1) |
| HSTX_EN_LN0 | 0 (0b0) |
| HSTX_EN_LN1 | 0 (0b0) |
| HSTX_EN_LN2 | 0 (0b0) |
| HSTX_EN_LN3 | 0 (0b0) |
| HSTX_EN_LNCK | 0 (0b0) |
| HYST_NCTL | 1 (0b01) |
| HYST_PCTL | 1 (0b01) |
| IBIAS_TEST_EN | 0 (0b0) |
| LANE_DIV_SEL | 0 (0b00) |
| LB_CH_SEL | 0 (0b0) |
| LB_EN_LN0 | 0 (0b0) |
| LB_EN_LN1 | 0 (0b0) |
| LB_EN_LN2 | 0 (0b0) |
| LB_EN_LN3 | 0 (0b0) |
| LB_EN_LNCK | 0 (0b0) |
| LB_POLAR_LN0 | 0 (0b0) |
| LB_POLAR_LN1 | 0 (0b0) |
| LB_POLAR_LN2 | 0 (0b0) |
| LB_POLAR_LN3 | 0 (0b0) |
| LB_POLAR_LNCK | 0 (0b0) |
| LOW_LPRX_VTH | 0 (0b0) |
| LPBKTST_EN | 0 (0b0000) |
| LPBKTST_EN_CK | 0 (0b0) |
| LPBK_DATA2TO1 | 0 (0b0000) |
| LPBK_DATA2TO1_CK | 0 (0b0) |
| LPBK_EN | 0 (0b0) |
| LPBK_SEL | 0 (0b0000) |
| LPRX_EN | 1 (0b1) |
| LPRX_TST | 0 (0b0000) |
| LPRX_TST_CK | 0 (0b0) |
| LPTX_DAT_POLAR_LN0 | 0 (0b0) |
| LPTX_DAT_POLAR_LN1 | 0 (0b0) |
| LPTX_DAT_POLAR_LN2 | 0 (0b0) |
| LPTX_DAT_POLAR_LN3 | 0 (0b0) |
| LPTX_DAT_POLAR_LNCK | 0 (0b0) |
| LPTX_EN_LN0 | 1 (0b1) |
| LPTX_EN_LN1 | 1 (0b1) |
| LPTX_EN_LN2 | 1 (0b1) |
| LPTX_EN_LN3 | 1 (0b1) |
| LPTX_EN_LNCK | 1 (0b1) |
| LPTX_NIMP_LN0 | 4 (0b100) |
| LPTX_NIMP_LN1 | 4 (0b100) |
| LPTX_NIMP_LN2 | 4 (0b100) |
| LPTX_NIMP_LN3 | 4 (0b100) |
| LPTX_NIMP_LNCK | 4 (0b100) |
| LPTX_PIMP_LN0 | 4 (0b100) |
| LPTX_PIMP_LN1 | 4 (0b100) |
| LPTX_PIMP_LN2 | 4 (0b100) |
| LPTX_PIMP_LN3 | 4 (0b100) |
| LPTX_PIMP_LNCK | 4 (0b100) |
| MIPI_PMA_DIS_N | 1 (0b1) |
| PGA_BIAS_LANE0 | 8 (0b1000) |
| PGA_BIAS_LANE1 | 8 (0b1000) |
| PGA_BIAS_LANE2 | 8 (0b1000) |
| PGA_BIAS_LANE3 | 8 (0b1000) |
| PGA_BIAS_LANECK | 8 (0b1000) |
| PGA_GAIN_LANE0 | 8 (0b1000) |
| PGA_GAIN_LANE1 | 8 (0b1000) |
| PGA_GAIN_LANE2 | 8 (0b1000) |
| PGA_GAIN_LANE3 | 8 (0b1000) |
| PGA_GAIN_LANECK | 8 (0b1000) |
| RX_ALIGN_BYTE | 184 (0b10111000) |
| RX_BYTE_LITTLE_ENDIAN | 1 (0b1) |
| RX_CLK_1X_SYNC_SEL | 0 (0b0) |
| RX_HS_8BIT_MODE | 0 (0b0) |
| RX_INVERT | 0 (0b0) |
| RX_LANE_ALIGN_EN | 0 (0b0) |
| RX_ODT_TRIM_LANE0 | 8 (0b1000) |
| RX_ODT_TRIM_LANE1 | 8 (0b1000) |
| RX_ODT_TRIM_LANE2 | 8 (0b1000) |
| RX_ODT_TRIM_LANE3 | 8 (0b1000) |
| RX_ODT_TRIM_LANECK | 8 (0b1000) |
| RX_ONE_BYTE0_MATCH | 0 (0b0) |
| RX_RD_START_DEPTH | 1 (0b00001) |
| RX_SYNC_MODE | 0 (0b0) |
| RX_WORD_ALIGN_BYPASS | 0 (0b0) |
| RX_WORD_ALIGN_DATA_VLD_SRC_SEL | 0 (0b0) |
| RX_WORD_LITTLE_ENDIAN | 1 (0b1) |
| SLEWN_CTL_LN0 | 15 (0b1111) |
| SLEWN_CTL_LN1 | 15 (0b1111) |
| SLEWN_CTL_LN2 | 15 (0b1111) |
| SLEWN_CTL_LN3 | 15 (0b1111) |
| SLEWN_CTL_LNCK | 15 (0b1111) |
| SLEWP_CTL_LN0 | 15 (0b1111) |
| SLEWP_CTL_LN1 | 15 (0b1111) |
| SLEWP_CTL_LN2 | 15 (0b1111) |
| SLEWP_CTL_LN3 | 15 (0b1111) |
| SLEWP_CTL_LNCK | 15 (0b1111) |
| SPLL_DIV_SEL | 0 (0b00) |
| STP_UNIT | 1 (0b01) |
| TERMN_CTL_LN0 | 8 (0b1000) |
| TERMN_CTL_LN1 | 8 (0b1000) |
| TERMN_CTL_LN2 | 8 (0b1000) |
| TERMN_CTL_LN3 | 8 (0b1000) |
| TERMN_CTL_LNCK | 8 (0b1000) |
| TERMP_CTL_LN0 | 8 (0b1000) |
| TERMP_CTL_LN1 | 8 (0b1000) |
| TERMP_CTL_LN2 | 8 (0b1000) |
| TERMP_CTL_LN3 | 8 (0b1000) |
| TERMP_CTL_LNCK | 8 (0b1000) |
| TEST_EN_LN0 | 0 (0b0) |
| TEST_EN_LN1 | 0 (0b0) |
| TEST_EN_LN2 | 0 (0b0) |
| TEST_EN_LN3 | 0 (0b0) |
| TEST_EN_LNCK | 0 (0b0) |
| TEST_N_IMP_LN0 | 0 (0b0) |
| TEST_N_IMP_LN1 | 0 (0b0) |
| TEST_N_IMP_LN2 | 0 (0b0) |
| TEST_N_IMP_LN3 | 0 (0b0) |
| TEST_N_IMP_LNCK | 0 (0b0) |
| TEST_P_IMP_LN0 | 0 (0b0) |
| TEST_P_IMP_LN1 | 0 (0b0) |
| TEST_P_IMP_LN2 | 0 (0b0) |
| TEST_P_IMP_LN3 | 0 (0b0) |
| TEST_P_IMP_LNCK | 0 (0b0) |
| TXDP_EN_LN0 | 0 (0b0) |
| TXDP_EN_LN1 | 0 (0b0) |
| TXDP_EN_LN2 | 0 (0b0) |
| TXDP_EN_LN3 | 0 (0b0) |
| TXDP_EN_LNCK | 0 (0b0) |
| TX_BYPASS_MODE | 0 (0b0) |
| TX_BYTECLK_SYNC_MODE | 0 (0b0) |
| TX_HS_8BIT_MODE | 0 (0b0) |
| TX_OCLK_USE_CIBCLK | 0 (0b0) |
| TX_PLLCLK | NONE |
| TX_RD_START_DEPTH | 1 (0b00001) |
| TX_SYNC_MODE | 0 (0b0) |
| TX_WORD_LITTLE_ENDIAN | 1 (0b1) |
MIPI_DPHYA #(
.ALP_ED_EN_LANE0(ALP_ED_EN_LANE0),
.ALP_ED_EN_LANE1(ALP_ED_EN_LANE1),
.ALP_ED_EN_LANE2(ALP_ED_EN_LANE2),
.ALP_ED_EN_LANE3(ALP_ED_EN_LANE3),
.ALP_ED_EN_LANECK(ALP_ED_EN_LANECK),
.ALP_ED_TST_LANE0(ALP_ED_TST_LANE0),
.ALP_ED_TST_LANE1(ALP_ED_TST_LANE1),
.ALP_ED_TST_LANE2(ALP_ED_TST_LANE2),
.ALP_ED_TST_LANE3(ALP_ED_TST_LANE3),
.ALP_ED_TST_LANECK(ALP_ED_TST_LANECK),
.ALP_EN_LN0(ALP_EN_LN0),
.ALP_EN_LN1(ALP_EN_LN1),
.ALP_EN_LN2(ALP_EN_LN2),
.ALP_EN_LN3(ALP_EN_LN3),
.ALP_EN_LNCK(ALP_EN_LNCK),
.ALP_HYS_EN_LANE0(ALP_HYS_EN_LANE0),
.ALP_HYS_EN_LANE1(ALP_HYS_EN_LANE1),
.ALP_HYS_EN_LANE2(ALP_HYS_EN_LANE2),
.ALP_HYS_EN_LANE3(ALP_HYS_EN_LANE3),
.ALP_HYS_EN_LANECK(ALP_HYS_EN_LANECK),
.ALP_TH_LANE0(ALP_TH_LANE0),
.ALP_TH_LANE1(ALP_TH_LANE1),
.ALP_TH_LANE2(ALP_TH_LANE2),
.ALP_TH_LANE3(ALP_TH_LANE3),
.ALP_TH_LANECK(ALP_TH_LANECK),
.ANA_BYTECLK_PH(ANA_BYTECLK_PH),
.BIT_REVERSE_LN0(BIT_REVERSE_LN0),
.BIT_REVERSE_LN1(BIT_REVERSE_LN1),
.BIT_REVERSE_LN2(BIT_REVERSE_LN2),
.BIT_REVERSE_LN3(BIT_REVERSE_LN3),
.BIT_REVERSE_LNCK(BIT_REVERSE_LNCK),
.BYPASS_TXHCLKEN(BYPASS_TXHCLKEN),
.BYPASS_TXHCLKEN_SYNC(BYPASS_TXHCLKEN_SYNC),
.BYTE_CLK_POLAR(BYTE_CLK_POLAR),
.BYTE_REVERSE_LN0(BYTE_REVERSE_LN0),
.BYTE_REVERSE_LN1(BYTE_REVERSE_LN1),
.BYTE_REVERSE_LN2(BYTE_REVERSE_LN2),
.BYTE_REVERSE_LN3(BYTE_REVERSE_LN3),
.BYTE_REVERSE_LNCK(BYTE_REVERSE_LNCK),
.CKLN_DELAY_EN(CKLN_DELAY_EN),
.CKLN_DELAY_OVR_VAL(CKLN_DELAY_OVR_VAL),
.D0LN_DELAY_EN(D0LN_DELAY_EN),
.D0LN_DELAY_OVR_VAL(D0LN_DELAY_OVR_VAL),
.D0LN_DESKEW_BYPASS(D0LN_DESKEW_BYPASS),
.D1LN_DELAY_EN(D1LN_DELAY_EN),
.D1LN_DELAY_OVR_VAL(D1LN_DELAY_OVR_VAL),
.D1LN_DESKEW_BYPASS(D1LN_DESKEW_BYPASS),
.D2LN_DELAY_EN(D2LN_DELAY_EN),
.D2LN_DELAY_OVR_VAL(D2LN_DELAY_OVR_VAL),
.D2LN_DESKEW_BYPASS(D2LN_DESKEW_BYPASS),
.D3LN_DELAY_EN(D3LN_DELAY_EN),
.D3LN_DELAY_OVR_VAL(D3LN_DELAY_OVR_VAL),
.D3LN_DESKEW_BYPASS(D3LN_DESKEW_BYPASS),
.DESKEW_EN_LOW_DELAY(DESKEW_EN_LOW_DELAY),
.DESKEW_EN_ONE_EDGE(DESKEW_EN_ONE_EDGE),
.DESKEW_FAST_LOOP_TIME(DESKEW_FAST_LOOP_TIME),
.DESKEW_FAST_MODE(DESKEW_FAST_MODE),
.DESKEW_HALF_OPENING(DESKEW_HALF_OPENING),
.DESKEW_LSB_MODE(DESKEW_LSB_MODE),
.DESKEW_M(DESKEW_M),
.DESKEW_MAX_SETTING(DESKEW_MAX_SETTING),
.DESKEW_M_TH(DESKEW_M_TH),
.DESKEW_ONE_CLK_EDGE_EN(DESKEW_ONE_CLK_EDGE_EN),
.DESKEW_RST_BYPASS(DESKEW_RST_BYPASS),
.DPHY_CK_SEL(DPHY_CK_SEL),
.EN_CLKB1X(EN_CLKB1X),
.EQ_CS_LANE0(EQ_CS_LANE0),
.EQ_CS_LANE1(EQ_CS_LANE1),
.EQ_CS_LANE2(EQ_CS_LANE2),
.EQ_CS_LANE3(EQ_CS_LANE3),
.EQ_CS_LANECK(EQ_CS_LANECK),
.EQ_PBIAS_LANE0(EQ_PBIAS_LANE0),
.EQ_PBIAS_LANE1(EQ_PBIAS_LANE1),
.EQ_PBIAS_LANE2(EQ_PBIAS_LANE2),
.EQ_PBIAS_LANE3(EQ_PBIAS_LANE3),
.EQ_PBIAS_LANECK(EQ_PBIAS_LANECK),
.EQ_RS_LANE0(EQ_RS_LANE0),
.EQ_RS_LANE1(EQ_RS_LANE1),
.EQ_RS_LANE2(EQ_RS_LANE2),
.EQ_RS_LANE3(EQ_RS_LANE3),
.EQ_RS_LANECK(EQ_RS_LANECK),
.EQ_ZLD_LANE0(EQ_ZLD_LANE0),
.EQ_ZLD_LANE1(EQ_ZLD_LANE1),
.EQ_ZLD_LANE2(EQ_ZLD_LANE2),
.EQ_ZLD_LANE3(EQ_ZLD_LANE3),
.EQ_ZLD_LANECK(EQ_ZLD_LANECK),
.HIGH_BW_LANE0(HIGH_BW_LANE0),
.HIGH_BW_LANE1(HIGH_BW_LANE1),
.HIGH_BW_LANE2(HIGH_BW_LANE2),
.HIGH_BW_LANE3(HIGH_BW_LANE3),
.HIGH_BW_LANECK(HIGH_BW_LANECK),
.HSCLK_LANE_LN0(HSCLK_LANE_LN0),
.HSCLK_LANE_LN1(HSCLK_LANE_LN1),
.HSCLK_LANE_LN2(HSCLK_LANE_LN2),
.HSCLK_LANE_LN3(HSCLK_LANE_LN3),
.HSCLK_LANE_LNCK(HSCLK_LANE_LNCK),
.HSREG_EN_LN0(HSREG_EN_LN0),
.HSREG_EN_LN1(HSREG_EN_LN1),
.HSREG_EN_LN2(HSREG_EN_LN2),
.HSREG_EN_LN3(HSREG_EN_LN3),
.HSREG_EN_LNCK(HSREG_EN_LNCK),
.HSREG_VREF_CTL(HSREG_VREF_CTL),
.HSREG_VREF_EN(HSREG_VREF_EN),
.HSRX_DLY_CTL_CK(HSRX_DLY_CTL_CK),
.HSRX_DLY_CTL_LANE0(HSRX_DLY_CTL_LANE0),
.HSRX_DLY_CTL_LANE1(HSRX_DLY_CTL_LANE1),
.HSRX_DLY_CTL_LANE2(HSRX_DLY_CTL_LANE2),
.HSRX_DLY_CTL_LANE3(HSRX_DLY_CTL_LANE3),
.HSRX_DLY_SEL_LANE0(HSRX_DLY_SEL_LANE0),
.HSRX_DLY_SEL_LANE1(HSRX_DLY_SEL_LANE1),
.HSRX_DLY_SEL_LANE2(HSRX_DLY_SEL_LANE2),
.HSRX_DLY_SEL_LANE3(HSRX_DLY_SEL_LANE3),
.HSRX_DLY_SEL_LANECK(HSRX_DLY_SEL_LANECK),
.HSRX_DUTY_LANE0(HSRX_DUTY_LANE0),
.HSRX_DUTY_LANE1(HSRX_DUTY_LANE1),
.HSRX_DUTY_LANE2(HSRX_DUTY_LANE2),
.HSRX_DUTY_LANE3(HSRX_DUTY_LANE3),
.HSRX_DUTY_LANECK(HSRX_DUTY_LANECK),
.HSRX_EN(HSRX_EN),
.HSRX_EQ_EN_LANE0(HSRX_EQ_EN_LANE0),
.HSRX_EQ_EN_LANE1(HSRX_EQ_EN_LANE1),
.HSRX_EQ_EN_LANE2(HSRX_EQ_EN_LANE2),
.HSRX_EQ_EN_LANE3(HSRX_EQ_EN_LANE3),
.HSRX_EQ_EN_LANECK(HSRX_EQ_EN_LANECK),
.HSRX_IBIAS(HSRX_IBIAS),
.HSRX_IBIAS_TEST_EN(HSRX_IBIAS_TEST_EN),
.HSRX_IMARG_EN(HSRX_IMARG_EN),
.HSRX_LANESEL(HSRX_LANESEL),
.HSRX_LANESEL_CK(HSRX_LANESEL_CK),
.HSRX_ODT_EN(HSRX_ODT_EN),
.HSRX_ODT_TST(HSRX_ODT_TST),
.HSRX_ODT_TST_CK(HSRX_ODT_TST_CK),
.HSRX_SEL(HSRX_SEL),
.HSRX_STOP_EN(HSRX_STOP_EN),
.HSRX_TST(HSRX_TST),
.HSRX_TST_CK(HSRX_TST_CK),
.HSRX_WAIT4EDGE(HSRX_WAIT4EDGE),
.HSTX_EN_LN0(HSTX_EN_LN0),
.HSTX_EN_LN1(HSTX_EN_LN1),
.HSTX_EN_LN2(HSTX_EN_LN2),
.HSTX_EN_LN3(HSTX_EN_LN3),
.HSTX_EN_LNCK(HSTX_EN_LNCK),
.HYST_NCTL(HYST_NCTL),
.HYST_PCTL(HYST_PCTL),
.IBIAS_TEST_EN(IBIAS_TEST_EN),
.LANE_DIV_SEL(LANE_DIV_SEL),
.LB_CH_SEL(LB_CH_SEL),
.LB_EN_LN0(LB_EN_LN0),
.LB_EN_LN1(LB_EN_LN1),
.LB_EN_LN2(LB_EN_LN2),
.LB_EN_LN3(LB_EN_LN3),
.LB_EN_LNCK(LB_EN_LNCK),
.LB_POLAR_LN0(LB_POLAR_LN0),
.LB_POLAR_LN1(LB_POLAR_LN1),
.LB_POLAR_LN2(LB_POLAR_LN2),
.LB_POLAR_LN3(LB_POLAR_LN3),
.LB_POLAR_LNCK(LB_POLAR_LNCK),
.LOW_LPRX_VTH(LOW_LPRX_VTH),
.LPBKTST_EN(LPBKTST_EN),
.LPBKTST_EN_CK(LPBKTST_EN_CK),
.LPBK_DATA2TO1(LPBK_DATA2TO1),
.LPBK_DATA2TO1_CK(LPBK_DATA2TO1_CK),
.LPBK_EN(LPBK_EN),
.LPBK_SEL(LPBK_SEL),
.LPRX_EN(LPRX_EN),
.LPRX_TST(LPRX_TST),
.LPRX_TST_CK(LPRX_TST_CK),
.LPTX_DAT_POLAR_LN0(LPTX_DAT_POLAR_LN0),
.LPTX_DAT_POLAR_LN1(LPTX_DAT_POLAR_LN1),
.LPTX_DAT_POLAR_LN2(LPTX_DAT_POLAR_LN2),
.LPTX_DAT_POLAR_LN3(LPTX_DAT_POLAR_LN3),
.LPTX_DAT_POLAR_LNCK(LPTX_DAT_POLAR_LNCK),
.LPTX_EN_LN0(LPTX_EN_LN0),
.LPTX_EN_LN1(LPTX_EN_LN1),
.LPTX_EN_LN2(LPTX_EN_LN2),
.LPTX_EN_LN3(LPTX_EN_LN3),
.LPTX_EN_LNCK(LPTX_EN_LNCK),
.LPTX_NIMP_LN0(LPTX_NIMP_LN0),
.LPTX_NIMP_LN1(LPTX_NIMP_LN1),
.LPTX_NIMP_LN2(LPTX_NIMP_LN2),
.LPTX_NIMP_LN3(LPTX_NIMP_LN3),
.LPTX_NIMP_LNCK(LPTX_NIMP_LNCK),
.LPTX_PIMP_LN0(LPTX_PIMP_LN0),
.LPTX_PIMP_LN1(LPTX_PIMP_LN1),
.LPTX_PIMP_LN2(LPTX_PIMP_LN2),
.LPTX_PIMP_LN3(LPTX_PIMP_LN3),
.LPTX_PIMP_LNCK(LPTX_PIMP_LNCK),
.MIPI_PMA_DIS_N(MIPI_PMA_DIS_N),
.PGA_BIAS_LANE0(PGA_BIAS_LANE0),
.PGA_BIAS_LANE1(PGA_BIAS_LANE1),
.PGA_BIAS_LANE2(PGA_BIAS_LANE2),
.PGA_BIAS_LANE3(PGA_BIAS_LANE3),
.PGA_BIAS_LANECK(PGA_BIAS_LANECK),
.PGA_GAIN_LANE0(PGA_GAIN_LANE0),
.PGA_GAIN_LANE1(PGA_GAIN_LANE1),
.PGA_GAIN_LANE2(PGA_GAIN_LANE2),
.PGA_GAIN_LANE3(PGA_GAIN_LANE3),
.PGA_GAIN_LANECK(PGA_GAIN_LANECK),
.RX_ALIGN_BYTE(RX_ALIGN_BYTE),
.RX_BYTE_LITTLE_ENDIAN(RX_BYTE_LITTLE_ENDIAN),
.RX_CLK_1X_SYNC_SEL(RX_CLK_1X_SYNC_SEL),
.RX_HS_8BIT_MODE(RX_HS_8BIT_MODE),
.RX_INVERT(RX_INVERT),
.RX_LANE_ALIGN_EN(RX_LANE_ALIGN_EN),
.RX_ODT_TRIM_LANE0(RX_ODT_TRIM_LANE0),
.RX_ODT_TRIM_LANE1(RX_ODT_TRIM_LANE1),
.RX_ODT_TRIM_LANE2(RX_ODT_TRIM_LANE2),
.RX_ODT_TRIM_LANE3(RX_ODT_TRIM_LANE3),
.RX_ODT_TRIM_LANECK(RX_ODT_TRIM_LANECK),
.RX_ONE_BYTE0_MATCH(RX_ONE_BYTE0_MATCH),
.RX_RD_START_DEPTH(RX_RD_START_DEPTH),
.RX_SYNC_MODE(RX_SYNC_MODE),
.RX_WORD_ALIGN_BYPASS(RX_WORD_ALIGN_BYPASS),
.RX_WORD_ALIGN_DATA_VLD_SRC_SEL(RX_WORD_ALIGN_DATA_VLD_SRC_SEL),
.RX_WORD_LITTLE_ENDIAN(RX_WORD_LITTLE_ENDIAN),
.SLEWN_CTL_LN0(SLEWN_CTL_LN0),
.SLEWN_CTL_LN1(SLEWN_CTL_LN1),
.SLEWN_CTL_LN2(SLEWN_CTL_LN2),
.SLEWN_CTL_LN3(SLEWN_CTL_LN3),
.SLEWN_CTL_LNCK(SLEWN_CTL_LNCK),
.SLEWP_CTL_LN0(SLEWP_CTL_LN0),
.SLEWP_CTL_LN1(SLEWP_CTL_LN1),
.SLEWP_CTL_LN2(SLEWP_CTL_LN2),
.SLEWP_CTL_LN3(SLEWP_CTL_LN3),
.SLEWP_CTL_LNCK(SLEWP_CTL_LNCK),
.SPLL_DIV_SEL(SPLL_DIV_SEL),
.STP_UNIT(STP_UNIT),
.TERMN_CTL_LN0(TERMN_CTL_LN0),
.TERMN_CTL_LN1(TERMN_CTL_LN1),
.TERMN_CTL_LN2(TERMN_CTL_LN2),
.TERMN_CTL_LN3(TERMN_CTL_LN3),
.TERMN_CTL_LNCK(TERMN_CTL_LNCK),
.TERMP_CTL_LN0(TERMP_CTL_LN0),
.TERMP_CTL_LN1(TERMP_CTL_LN1),
.TERMP_CTL_LN2(TERMP_CTL_LN2),
.TERMP_CTL_LN3(TERMP_CTL_LN3),
.TERMP_CTL_LNCK(TERMP_CTL_LNCK),
.TEST_EN_LN0(TEST_EN_LN0),
.TEST_EN_LN1(TEST_EN_LN1),
.TEST_EN_LN2(TEST_EN_LN2),
.TEST_EN_LN3(TEST_EN_LN3),
.TEST_EN_LNCK(TEST_EN_LNCK),
.TEST_N_IMP_LN0(TEST_N_IMP_LN0),
.TEST_N_IMP_LN1(TEST_N_IMP_LN1),
.TEST_N_IMP_LN2(TEST_N_IMP_LN2),
.TEST_N_IMP_LN3(TEST_N_IMP_LN3),
.TEST_N_IMP_LNCK(TEST_N_IMP_LNCK),
.TEST_P_IMP_LN0(TEST_P_IMP_LN0),
.TEST_P_IMP_LN1(TEST_P_IMP_LN1),
.TEST_P_IMP_LN2(TEST_P_IMP_LN2),
.TEST_P_IMP_LN3(TEST_P_IMP_LN3),
.TEST_P_IMP_LNCK(TEST_P_IMP_LNCK),
.TXDP_EN_LN0(TXDP_EN_LN0),
.TXDP_EN_LN1(TXDP_EN_LN1),
.TXDP_EN_LN2(TXDP_EN_LN2),
.TXDP_EN_LN3(TXDP_EN_LN3),
.TXDP_EN_LNCK(TXDP_EN_LNCK),
.TX_BYPASS_MODE(TX_BYPASS_MODE),
.TX_BYTECLK_SYNC_MODE(TX_BYTECLK_SYNC_MODE),
.TX_HS_8BIT_MODE(TX_HS_8BIT_MODE),
.TX_OCLK_USE_CIBCLK(TX_OCLK_USE_CIBCLK),
.TX_PLLCLK(TX_PLLCLK),
.TX_RD_START_DEPTH(TX_RD_START_DEPTH),
.TX_SYNC_MODE(TX_SYNC_MODE),
.TX_WORD_LITTLE_ENDIAN(TX_WORD_LITTLE_ENDIAN)
) mipi_dphya_inst (
.ALPEDO_LANE0(ALPEDO_LANE0),
.ALPEDO_LANE1(ALPEDO_LANE1),
.ALPEDO_LANE2(ALPEDO_LANE2),
.ALPEDO_LANE3(ALPEDO_LANE3),
.ALPEDO_LANECK(ALPEDO_LANECK),
.ALPEN_LN0(ALPEN_LN0),
.ALPEN_LN1(ALPEN_LN1),
.ALPEN_LN2(ALPEN_LN2),
.ALPEN_LN3(ALPEN_LN3),
.ALPEN_LNCK(ALPEN_LNCK),
.ALP_EDEN_LANE0(ALP_EDEN_LANE0),
.ALP_EDEN_LANE1(ALP_EDEN_LANE1),
.ALP_EDEN_LANE2(ALP_EDEN_LANE2),
.ALP_EDEN_LANE3(ALP_EDEN_LANE3),
.ALP_EDEN_LANECK(ALP_EDEN_LANECK),
.CK0(CK0),
.CK180(CK180),
.CK270(CK270),
.CK90(CK90),
.CKLN_HSTXD(CKLN_HSTXD),
.CK_N(CK_N),
.CK_P(CK_P),
.D0LN_DESKEW_DONE(D0LN_DESKEW_DONE),
.D0LN_DESKEW_ERROR(D0LN_DESKEW_ERROR),
.D0LN_DESKEW_REQ(D0LN_DESKEW_REQ),
.D0LN_HSRXD(D0LN_HSRXD),
.D0LN_HSRXD_VLD(D0LN_HSRXD_VLD),
.D0LN_HSRX_DREN(D0LN_HSRX_DREN),
.D0LN_HSTXD(D0LN_HSTXD),
.D0_N(D0_N),
.D0_P(D0_P),
.D1LN_DESKEW_DONE(D1LN_DESKEW_DONE),
.D1LN_DESKEW_ERROR(D1LN_DESKEW_ERROR),
.D1LN_DESKEW_REQ(D1LN_DESKEW_REQ),
.D1LN_HSRXD(D1LN_HSRXD),
.D1LN_HSRXD_VLD(D1LN_HSRXD_VLD),
.D1LN_HSRX_DREN(D1LN_HSRX_DREN),
.D1LN_HSTXD(D1LN_HSTXD),
.D1_N(D1_N),
.D1_P(D1_P),
.D2LN_DESKEW_DONE(D2LN_DESKEW_DONE),
.D2LN_DESKEW_ERROR(D2LN_DESKEW_ERROR),
.D2LN_DESKEW_REQ(D2LN_DESKEW_REQ),
.D2LN_HSRXD(D2LN_HSRXD),
.D2LN_HSRXD_VLD(D2LN_HSRXD_VLD),
.D2LN_HSRX_DREN(D2LN_HSRX_DREN),
.D2LN_HSTXD(D2LN_HSTXD),
.D2_N(D2_N),
.D2_P(D2_P),
.D3LN_DESKEW_DONE(D3LN_DESKEW_DONE),
.D3LN_DESKEW_ERROR(D3LN_DESKEW_ERROR),
.D3LN_DESKEW_REQ(D3LN_DESKEW_REQ),
.D3LN_HSRXD(D3LN_HSRXD),
.D3LN_HSRXD_VLD(D3LN_HSRXD_VLD),
.D3LN_HSRX_DREN(D3LN_HSRX_DREN),
.D3LN_HSTXD(D3LN_HSTXD),
.D3_N(D3_N),
.D3_P(D3_P),
.DI_LPRX0_N(DI_LPRX0_N),
.DI_LPRX0_P(DI_LPRX0_P),
.DI_LPRX1_N(DI_LPRX1_N),
.DI_LPRX1_P(DI_LPRX1_P),
.DI_LPRX2_N(DI_LPRX2_N),
.DI_LPRX2_P(DI_LPRX2_P),
.DI_LPRX3_N(DI_LPRX3_N),
.DI_LPRX3_P(DI_LPRX3_P),
.DI_LPRXCK_N(DI_LPRXCK_N),
.DI_LPRXCK_P(DI_LPRXCK_P),
.DO_LPTX0_N(DO_LPTX0_N),
.DO_LPTX0_P(DO_LPTX0_P),
.DO_LPTX1_N(DO_LPTX1_N),
.DO_LPTX1_P(DO_LPTX1_P),
.DO_LPTX2_N(DO_LPTX2_N),
.DO_LPTX2_P(DO_LPTX2_P),
.DO_LPTX3_N(DO_LPTX3_N),
.DO_LPTX3_P(DO_LPTX3_P),
.DO_LPTXCK_N(DO_LPTXCK_N),
.DO_LPTXCK_P(DO_LPTXCK_P),
.HSRX_DLYDIR_LANE0(HSRX_DLYDIR_LANE0),
.HSRX_DLYDIR_LANE1(HSRX_DLYDIR_LANE1),
.HSRX_DLYDIR_LANE2(HSRX_DLYDIR_LANE2),
.HSRX_DLYDIR_LANE3(HSRX_DLYDIR_LANE3),
.HSRX_DLYDIR_LANECK(HSRX_DLYDIR_LANECK),
.HSRX_DLYLDN_LANE0(HSRX_DLYLDN_LANE0),
.HSRX_DLYLDN_LANE1(HSRX_DLYLDN_LANE1),
.HSRX_DLYLDN_LANE2(HSRX_DLYLDN_LANE2),
.HSRX_DLYLDN_LANE3(HSRX_DLYLDN_LANE3),
.HSRX_DLYLDN_LANECK(HSRX_DLYLDN_LANECK),
.HSRX_DLYMV_LANE0(HSRX_DLYMV_LANE0),
.HSRX_DLYMV_LANE1(HSRX_DLYMV_LANE1),
.HSRX_DLYMV_LANE2(HSRX_DLYMV_LANE2),
.HSRX_DLYMV_LANE3(HSRX_DLYMV_LANE3),
.HSRX_DLYMV_LANECK(HSRX_DLYMV_LANECK),
.HSRX_EN_CK(HSRX_EN_CK),
.HSRX_EN_D0(HSRX_EN_D0),
.HSRX_EN_D1(HSRX_EN_D1),
.HSRX_EN_D2(HSRX_EN_D2),
.HSRX_EN_D3(HSRX_EN_D3),
.HSRX_ODTEN_CK(HSRX_ODTEN_CK),
.HSRX_STOP(HSRX_STOP),
.HSTXD_VLD(HSTXD_VLD),
.HSTXEN_LN0(HSTXEN_LN0),
.HSTXEN_LN1(HSTXEN_LN1),
.HSTXEN_LN2(HSTXEN_LN2),
.HSTXEN_LN3(HSTXEN_LN3),
.HSTXEN_LNCK(HSTXEN_LNCK),
.MA_INC(MA_INC),
.MCLK(MCLK),
.MOPCODE(MOPCODE),
.MRDATA(MRDATA),
.MWDATA(MWDATA),
.PWRON_RX(PWRON_RX),
.PWRON_TX(PWRON_TX),
.RESET(RESET),
.RX_CLK_1X(RX_CLK_1X),
.RX_CLK_O(RX_CLK_O),
.RX_DRST_N(RX_DRST_N),
.SPLL_CKN(SPLL_CKN),
.SPLL_CKP(SPLL_CKP),
.TXDPEN_LN0(TXDPEN_LN0),
.TXDPEN_LN1(TXDPEN_LN1),
.TXDPEN_LN2(TXDPEN_LN2),
.TXDPEN_LN3(TXDPEN_LN3),
.TXDPEN_LNCK(TXDPEN_LNCK),
.TXHCLK_EN(TXHCLK_EN),
.TX_CLK_1X(TX_CLK_1X),
.TX_CLK_O(TX_CLK_O),
.TX_DRST_N(TX_DRST_N),
.WALIGN_DVLD(WALIGN_DVLD)
);This device is not yet supported in Apicula
| Port | Size | Direction |
|---|---|---|
| BYTE_LENDIAN | 1 | input |
| CK_N | 1 | inout |
| CK_P | 1 | inout |
| D0LN_DESKEW_DONE | 1 | output |
| D0LN_HSRXD | 16 | output |
| D0LN_HSRXD_VLD | 1 | output |
| D0LN_HSRX_DREN | 1 | input |
| D1LN_DESKEW_DONE | 1 | output |
| D1LN_HSRXD | 16 | output |
| D1LN_HSRXD_VLD | 1 | output |
| D1LN_HSRX_DREN | 1 | input |
| D2LN_DESKEW_DONE | 1 | output |
| D2LN_HSRXD | 16 | output |
| D2LN_HSRXD_VLD | 1 | output |
| D2LN_HSRX_DREN | 1 | input |
| D3LN_DESKEW_DONE | 1 | output |
| D3LN_HSRXD | 16 | output |
| D3LN_HSRXD_VLD | 1 | output |
| D3LN_HSRX_DREN | 1 | input |
| DESKEW_BY | 1 | input |
| DESKEW_EN_OEDGE | 1 | input |
| DESKEW_ERROR | 1 | output |
| DESKEW_HALF_OPENING | 6 | input |
| DESKEW_LNSEL | 3 | input |
| DESKEW_LSB_MODE | 2 | input |
| DESKEW_M | 3 | input |
| DESKEW_MSET | 7 | input |
| DESKEW_MTH | 13 | input |
| DESKEW_OCLKEDG_EN | 1 | input |
| DESKEW_OWVAL | 7 | input |
| DESKEW_REQ | 1 | input |
| DI_LPRX0_N | 1 | output |
| DI_LPRX0_P | 1 | output |
| DI_LPRX1_N | 1 | output |
| DI_LPRX1_P | 1 | output |
| DI_LPRX2_N | 1 | output |
| DI_LPRX2_P | 1 | output |
| DI_LPRX3_N | 1 | output |
| DI_LPRX3_P | 1 | output |
| DI_LPRXCK_N | 1 | output |
| DI_LPRXCK_P | 1 | output |
| DO_LPTX0_N | 1 | input |
| DO_LPTX0_P | 1 | input |
| DO_LPTX1_N | 1 | input |
| DO_LPTX1_P | 1 | input |
| DO_LPTX2_N | 1 | input |
| DO_LPTX2_P | 1 | input |
| DO_LPTX3_N | 1 | input |
| DO_LPTX3_P | 1 | input |
| DO_LPTXCK_N | 1 | input |
| DO_LPTXCK_P | 1 | input |
| DRST_N | 1 | input |
| EQCS_CK | 3 | input |
| EQCS_LANE0 | 3 | input |
| EQCS_LANE1 | 3 | input |
| EQCS_LANE2 | 3 | input |
| EQCS_LANE3 | 3 | input |
| EQRS_CK | 3 | input |
| EQRS_LANE0 | 3 | input |
| EQRS_LANE1 | 3 | input |
| EQRS_LANE2 | 3 | input |
| EQRS_LANE3 | 3 | input |
| FIFO_RD_STD | 3 | input |
| HSRX_DLYDIR_CK | 1 | input |
| HSRX_DLYDIR_LANE0 | 1 | input |
| HSRX_DLYDIR_LANE1 | 1 | input |
| HSRX_DLYDIR_LANE2 | 1 | input |
| HSRX_DLYDIR_LANE3 | 1 | input |
| HSRX_DLYLDN_CK | 1 | input |
| HSRX_DLYLDN_LANE0 | 1 | input |
| HSRX_DLYLDN_LANE1 | 1 | input |
| HSRX_DLYLDN_LANE2 | 1 | input |
| HSRX_DLYLDN_LANE3 | 1 | input |
| HSRX_DLYMV_CK | 1 | input |
| HSRX_DLYMV_LANE0 | 1 | input |
| HSRX_DLYMV_LANE1 | 1 | input |
| HSRX_DLYMV_LANE2 | 1 | input |
| HSRX_DLYMV_LANE3 | 1 | input |
| HSRX_EN_CK | 1 | input |
| HSRX_ODTEN_CK | 1 | input |
| HSRX_ODTEN_D0 | 1 | input |
| HSRX_ODTEN_D1 | 1 | input |
| HSRX_ODTEN_D2 | 1 | input |
| HSRX_ODTEN_D3 | 1 | input |
| HSRX_STOP | 1 | input |
| HS_8BIT_MODE | 1 | input |
| LALIGN_EN | 1 | input |
| LPRX_EN_CK | 1 | input |
| LPRX_EN_D0 | 1 | input |
| LPRX_EN_D1 | 1 | input |
| LPRX_EN_D2 | 1 | input |
| LPRX_EN_D3 | 1 | input |
| LPTX_EN_CK | 1 | input |
| LPTX_EN_D0 | 1 | input |
| LPTX_EN_D1 | 1 | input |
| LPTX_EN_D2 | 1 | input |
| LPTX_EN_D3 | 1 | input |
| ONE_BYTE0_MATCH | 1 | input |
| PWRON | 1 | input |
| RESET | 1 | input |
| RX0_N | 1 | inout |
| RX0_P | 1 | inout |
| RX1_N | 1 | inout |
| RX1_P | 1 | inout |
| RX2_N | 1 | inout |
| RX2_P | 1 | inout |
| RX3_N | 1 | inout |
| RX3_P | 1 | inout |
| RX_CLK_1X | 1 | input |
| RX_CLK_O | 1 | output |
| RX_INVERT | 1 | input |
| WALIGN_BY | 1 | input |
| WALIGN_DVLD | 1 | input |
| WORD_LENDIAN | 1 | input |
| Parameter | Default Value |
|---|---|
| ALIGN_BYTE | 184 (0b10111000) |
| EN_CLKB1X | 1 (0b1) |
| EQ_ADPSEL_CK | 0 (0b0) |
| EQ_ADPSEL_LANE0 | 0 (0b0) |
| EQ_ADPSEL_LANE1 | 0 (0b0) |
| EQ_ADPSEL_LANE2 | 0 (0b0) |
| EQ_ADPSEL_LANE3 | 0 (0b0) |
| EQ_CS_CK | 4 (0b100) |
| EQ_CS_LANE0 | 4 (0b100) |
| EQ_CS_LANE1 | 4 (0b100) |
| EQ_CS_LANE2 | 4 (0b100) |
| EQ_CS_LANE3 | 4 (0b100) |
| EQ_PBIAS_CK | 4 (0b0100) |
| EQ_PBIAS_LANE0 | 4 (0b0100) |
| EQ_PBIAS_LANE1 | 4 (0b0100) |
| EQ_PBIAS_LANE2 | 4 (0b0100) |
| EQ_PBIAS_LANE3 | 4 (0b0100) |
| EQ_RS_CK | 4 (0b100) |
| EQ_RS_LANE0 | 4 (0b100) |
| EQ_RS_LANE1 | 4 (0b100) |
| EQ_RS_LANE2 | 4 (0b100) |
| EQ_RS_LANE3 | 4 (0b100) |
| EQ_ZLD_CK | 8 (0b1000) |
| EQ_ZLD_LANE0 | 8 (0b1000) |
| EQ_ZLD_LANE1 | 8 (0b1000) |
| EQ_ZLD_LANE2 | 8 (0b1000) |
| EQ_ZLD_LANE3 | 8 (0b1000) |
| HIGH_BW_CK | 1 (0b1) |
| HIGH_BW_LANE0 | 1 (0b1) |
| HIGH_BW_LANE1 | 1 (0b1) |
| HIGH_BW_LANE2 | 1 (0b1) |
| HIGH_BW_LANE3 | 1 (0b1) |
| HSRX_DLYCTL_CK | 0 (0b0000000) |
| HSRX_DLYCTL_LANE0 | 0 (0b0000000) |
| HSRX_DLYCTL_LANE1 | 0 (0b0000000) |
| HSRX_DLYCTL_LANE2 | 0 (0b0000000) |
| HSRX_DLYCTL_LANE3 | 0 (0b0000000) |
| HSRX_DLY_SEL | 0 (0b0) |
| HSRX_DUTY_CK | 8 (0b1000) |
| HSRX_DUTY_LANE0 | 8 (0b1000) |
| HSRX_DUTY_LANE1 | 8 (0b1000) |
| HSRX_DUTY_LANE2 | 8 (0b1000) |
| HSRX_DUTY_LANE3 | 8 (0b1000) |
| HSRX_EN | 1 (0b1) |
| HSRX_EQ_EN_CK | 1 (0b1) |
| HSRX_EQ_EN_LANE0 | 1 (0b1) |
| HSRX_EQ_EN_LANE1 | 1 (0b1) |
| HSRX_EQ_EN_LANE2 | 1 (0b1) |
| HSRX_EQ_EN_LANE3 | 1 (0b1) |
| HSRX_IBIAS | 3 (0b0011) |
| HSRX_IMARG_EN | 1 (0b1) |
| HSRX_ODT_EN | 1 (0b1) |
| HSRX_ODT_TST | 0 (0b0000) |
| HSRX_ODT_TST_CK | 0 (0b0) |
| HSRX_STOP_EN | 0 (0b0) |
| HSRX_TST | 0 (0b0000) |
| HSRX_TST_CK | 0 (0b0) |
| HSRX_WAIT4EDGE | 0 (0b0) |
| HYST_NCTL | 1 (0b01) |
| HYST_PCTL | 1 (0b01) |
| LOW_LPRX_VTH | 0 (0b0) |
| LPRX_EN | 1 (0b1) |
| LPRX_TST | 0 (0b0000) |
| LPRX_TST_CK | 0 (0b0) |
| LPTX_EN | 1 (0b1) |
| LPTX_SW_CK | 4 (0b100) |
| LPTX_SW_LANE0 | 4 (0b100) |
| LPTX_SW_LANE1 | 4 (0b100) |
| LPTX_SW_LANE2 | 4 (0b100) |
| LPTX_SW_LANE3 | 4 (0b100) |
| LPTX_TST | 0 (0b0000) |
| LPTX_TST_CK | 0 (0b0) |
| MIPI_CK_EN | 1 (0b1) |
| MIPI_DIS_N | 1 (0b1) |
| MIPI_LANE0_EN | 0 (0b0) |
| MIPI_LANE1_EN | 0 (0b0) |
| MIPI_LANE2_EN | 0 (0b0) |
| MIPI_LANE3_EN | 0 (0b0) |
| PGA_BIAS_CK | 8 (0b1000) |
| PGA_BIAS_LANE0 | 8 (0b1000) |
| PGA_BIAS_LANE1 | 8 (0b1000) |
| PGA_BIAS_LANE2 | 8 (0b1000) |
| PGA_BIAS_LANE3 | 8 (0b1000) |
| PGA_GAIN_CK | 8 (0b1000) |
| PGA_GAIN_LANE0 | 8 (0b1000) |
| PGA_GAIN_LANE1 | 8 (0b1000) |
| PGA_GAIN_LANE2 | 8 (0b1000) |
| PGA_GAIN_LANE3 | 8 (0b1000) |
| RX_CLK1X_SYNC_SEL | 0 (0b0) |
| RX_ODT_TRIM_CK | 7 (0b0111) |
| RX_ODT_TRIM_LANE0 | 7 (0b0111) |
| RX_ODT_TRIM_LANE1 | 7 (0b0111) |
| RX_ODT_TRIM_LANE2 | 7 (0b0111) |
| RX_ODT_TRIM_LANE3 | 7 (0b0111) |
| STP_UNIT | 0 (0b00) |
| SYNC_CLK_SEL | 1 (0b1) |
| WALIGN_DVLD_SRC_SEL | 0 (0b0) |
MIPI_DPHY_RX #(
.ALIGN_BYTE(ALIGN_BYTE),
.EN_CLKB1X(EN_CLKB1X),
.EQ_ADPSEL_CK(EQ_ADPSEL_CK),
.EQ_ADPSEL_LANE0(EQ_ADPSEL_LANE0),
.EQ_ADPSEL_LANE1(EQ_ADPSEL_LANE1),
.EQ_ADPSEL_LANE2(EQ_ADPSEL_LANE2),
.EQ_ADPSEL_LANE3(EQ_ADPSEL_LANE3),
.EQ_CS_CK(EQ_CS_CK),
.EQ_CS_LANE0(EQ_CS_LANE0),
.EQ_CS_LANE1(EQ_CS_LANE1),
.EQ_CS_LANE2(EQ_CS_LANE2),
.EQ_CS_LANE3(EQ_CS_LANE3),
.EQ_PBIAS_CK(EQ_PBIAS_CK),
.EQ_PBIAS_LANE0(EQ_PBIAS_LANE0),
.EQ_PBIAS_LANE1(EQ_PBIAS_LANE1),
.EQ_PBIAS_LANE2(EQ_PBIAS_LANE2),
.EQ_PBIAS_LANE3(EQ_PBIAS_LANE3),
.EQ_RS_CK(EQ_RS_CK),
.EQ_RS_LANE0(EQ_RS_LANE0),
.EQ_RS_LANE1(EQ_RS_LANE1),
.EQ_RS_LANE2(EQ_RS_LANE2),
.EQ_RS_LANE3(EQ_RS_LANE3),
.EQ_ZLD_CK(EQ_ZLD_CK),
.EQ_ZLD_LANE0(EQ_ZLD_LANE0),
.EQ_ZLD_LANE1(EQ_ZLD_LANE1),
.EQ_ZLD_LANE2(EQ_ZLD_LANE2),
.EQ_ZLD_LANE3(EQ_ZLD_LANE3),
.HIGH_BW_CK(HIGH_BW_CK),
.HIGH_BW_LANE0(HIGH_BW_LANE0),
.HIGH_BW_LANE1(HIGH_BW_LANE1),
.HIGH_BW_LANE2(HIGH_BW_LANE2),
.HIGH_BW_LANE3(HIGH_BW_LANE3),
.HSRX_DLYCTL_CK(HSRX_DLYCTL_CK),
.HSRX_DLYCTL_LANE0(HSRX_DLYCTL_LANE0),
.HSRX_DLYCTL_LANE1(HSRX_DLYCTL_LANE1),
.HSRX_DLYCTL_LANE2(HSRX_DLYCTL_LANE2),
.HSRX_DLYCTL_LANE3(HSRX_DLYCTL_LANE3),
.HSRX_DLY_SEL(HSRX_DLY_SEL),
.HSRX_DUTY_CK(HSRX_DUTY_CK),
.HSRX_DUTY_LANE0(HSRX_DUTY_LANE0),
.HSRX_DUTY_LANE1(HSRX_DUTY_LANE1),
.HSRX_DUTY_LANE2(HSRX_DUTY_LANE2),
.HSRX_DUTY_LANE3(HSRX_DUTY_LANE3),
.HSRX_EN(HSRX_EN),
.HSRX_EQ_EN_CK(HSRX_EQ_EN_CK),
.HSRX_EQ_EN_LANE0(HSRX_EQ_EN_LANE0),
.HSRX_EQ_EN_LANE1(HSRX_EQ_EN_LANE1),
.HSRX_EQ_EN_LANE2(HSRX_EQ_EN_LANE2),
.HSRX_EQ_EN_LANE3(HSRX_EQ_EN_LANE3),
.HSRX_IBIAS(HSRX_IBIAS),
.HSRX_IMARG_EN(HSRX_IMARG_EN),
.HSRX_ODT_EN(HSRX_ODT_EN),
.HSRX_ODT_TST(HSRX_ODT_TST),
.HSRX_ODT_TST_CK(HSRX_ODT_TST_CK),
.HSRX_STOP_EN(HSRX_STOP_EN),
.HSRX_TST(HSRX_TST),
.HSRX_TST_CK(HSRX_TST_CK),
.HSRX_WAIT4EDGE(HSRX_WAIT4EDGE),
.HYST_NCTL(HYST_NCTL),
.HYST_PCTL(HYST_PCTL),
.LOW_LPRX_VTH(LOW_LPRX_VTH),
.LPRX_EN(LPRX_EN),
.LPRX_TST(LPRX_TST),
.LPRX_TST_CK(LPRX_TST_CK),
.LPTX_EN(LPTX_EN),
.LPTX_SW_CK(LPTX_SW_CK),
.LPTX_SW_LANE0(LPTX_SW_LANE0),
.LPTX_SW_LANE1(LPTX_SW_LANE1),
.LPTX_SW_LANE2(LPTX_SW_LANE2),
.LPTX_SW_LANE3(LPTX_SW_LANE3),
.LPTX_TST(LPTX_TST),
.LPTX_TST_CK(LPTX_TST_CK),
.MIPI_CK_EN(MIPI_CK_EN),
.MIPI_DIS_N(MIPI_DIS_N),
.MIPI_LANE0_EN(MIPI_LANE0_EN),
.MIPI_LANE1_EN(MIPI_LANE1_EN),
.MIPI_LANE2_EN(MIPI_LANE2_EN),
.MIPI_LANE3_EN(MIPI_LANE3_EN),
.PGA_BIAS_CK(PGA_BIAS_CK),
.PGA_BIAS_LANE0(PGA_BIAS_LANE0),
.PGA_BIAS_LANE1(PGA_BIAS_LANE1),
.PGA_BIAS_LANE2(PGA_BIAS_LANE2),
.PGA_BIAS_LANE3(PGA_BIAS_LANE3),
.PGA_GAIN_CK(PGA_GAIN_CK),
.PGA_GAIN_LANE0(PGA_GAIN_LANE0),
.PGA_GAIN_LANE1(PGA_GAIN_LANE1),
.PGA_GAIN_LANE2(PGA_GAIN_LANE2),
.PGA_GAIN_LANE3(PGA_GAIN_LANE3),
.RX_CLK1X_SYNC_SEL(RX_CLK1X_SYNC_SEL),
.RX_ODT_TRIM_CK(RX_ODT_TRIM_CK),
.RX_ODT_TRIM_LANE0(RX_ODT_TRIM_LANE0),
.RX_ODT_TRIM_LANE1(RX_ODT_TRIM_LANE1),
.RX_ODT_TRIM_LANE2(RX_ODT_TRIM_LANE2),
.RX_ODT_TRIM_LANE3(RX_ODT_TRIM_LANE3),
.STP_UNIT(STP_UNIT),
.SYNC_CLK_SEL(SYNC_CLK_SEL),
.WALIGN_DVLD_SRC_SEL(WALIGN_DVLD_SRC_SEL)
) mipi_dphy_rx_inst (
.BYTE_LENDIAN(BYTE_LENDIAN),
.CK_N(CK_N),
.CK_P(CK_P),
.D0LN_DESKEW_DONE(D0LN_DESKEW_DONE),
.D0LN_HSRXD(D0LN_HSRXD),
.D0LN_HSRXD_VLD(D0LN_HSRXD_VLD),
.D0LN_HSRX_DREN(D0LN_HSRX_DREN),
.D1LN_DESKEW_DONE(D1LN_DESKEW_DONE),
.D1LN_HSRXD(D1LN_HSRXD),
.D1LN_HSRXD_VLD(D1LN_HSRXD_VLD),
.D1LN_HSRX_DREN(D1LN_HSRX_DREN),
.D2LN_DESKEW_DONE(D2LN_DESKEW_DONE),
.D2LN_HSRXD(D2LN_HSRXD),
.D2LN_HSRXD_VLD(D2LN_HSRXD_VLD),
.D2LN_HSRX_DREN(D2LN_HSRX_DREN),
.D3LN_DESKEW_DONE(D3LN_DESKEW_DONE),
.D3LN_HSRXD(D3LN_HSRXD),
.D3LN_HSRXD_VLD(D3LN_HSRXD_VLD),
.D3LN_HSRX_DREN(D3LN_HSRX_DREN),
.DESKEW_BY(DESKEW_BY),
.DESKEW_EN_OEDGE(DESKEW_EN_OEDGE),
.DESKEW_ERROR(DESKEW_ERROR),
.DESKEW_HALF_OPENING(DESKEW_HALF_OPENING),
.DESKEW_LNSEL(DESKEW_LNSEL),
.DESKEW_LSB_MODE(DESKEW_LSB_MODE),
.DESKEW_M(DESKEW_M),
.DESKEW_MSET(DESKEW_MSET),
.DESKEW_MTH(DESKEW_MTH),
.DESKEW_OCLKEDG_EN(DESKEW_OCLKEDG_EN),
.DESKEW_OWVAL(DESKEW_OWVAL),
.DESKEW_REQ(DESKEW_REQ),
.DI_LPRX0_N(DI_LPRX0_N),
.DI_LPRX0_P(DI_LPRX0_P),
.DI_LPRX1_N(DI_LPRX1_N),
.DI_LPRX1_P(DI_LPRX1_P),
.DI_LPRX2_N(DI_LPRX2_N),
.DI_LPRX2_P(DI_LPRX2_P),
.DI_LPRX3_N(DI_LPRX3_N),
.DI_LPRX3_P(DI_LPRX3_P),
.DI_LPRXCK_N(DI_LPRXCK_N),
.DI_LPRXCK_P(DI_LPRXCK_P),
.DO_LPTX0_N(DO_LPTX0_N),
.DO_LPTX0_P(DO_LPTX0_P),
.DO_LPTX1_N(DO_LPTX1_N),
.DO_LPTX1_P(DO_LPTX1_P),
.DO_LPTX2_N(DO_LPTX2_N),
.DO_LPTX2_P(DO_LPTX2_P),
.DO_LPTX3_N(DO_LPTX3_N),
.DO_LPTX3_P(DO_LPTX3_P),
.DO_LPTXCK_N(DO_LPTXCK_N),
.DO_LPTXCK_P(DO_LPTXCK_P),
.DRST_N(DRST_N),
.EQCS_CK(EQCS_CK),
.EQCS_LANE0(EQCS_LANE0),
.EQCS_LANE1(EQCS_LANE1),
.EQCS_LANE2(EQCS_LANE2),
.EQCS_LANE3(EQCS_LANE3),
.EQRS_CK(EQRS_CK),
.EQRS_LANE0(EQRS_LANE0),
.EQRS_LANE1(EQRS_LANE1),
.EQRS_LANE2(EQRS_LANE2),
.EQRS_LANE3(EQRS_LANE3),
.FIFO_RD_STD(FIFO_RD_STD),
.HSRX_DLYDIR_CK(HSRX_DLYDIR_CK),
.HSRX_DLYDIR_LANE0(HSRX_DLYDIR_LANE0),
.HSRX_DLYDIR_LANE1(HSRX_DLYDIR_LANE1),
.HSRX_DLYDIR_LANE2(HSRX_DLYDIR_LANE2),
.HSRX_DLYDIR_LANE3(HSRX_DLYDIR_LANE3),
.HSRX_DLYLDN_CK(HSRX_DLYLDN_CK),
.HSRX_DLYLDN_LANE0(HSRX_DLYLDN_LANE0),
.HSRX_DLYLDN_LANE1(HSRX_DLYLDN_LANE1),
.HSRX_DLYLDN_LANE2(HSRX_DLYLDN_LANE2),
.HSRX_DLYLDN_LANE3(HSRX_DLYLDN_LANE3),
.HSRX_DLYMV_CK(HSRX_DLYMV_CK),
.HSRX_DLYMV_LANE0(HSRX_DLYMV_LANE0),
.HSRX_DLYMV_LANE1(HSRX_DLYMV_LANE1),
.HSRX_DLYMV_LANE2(HSRX_DLYMV_LANE2),
.HSRX_DLYMV_LANE3(HSRX_DLYMV_LANE3),
.HSRX_EN_CK(HSRX_EN_CK),
.HSRX_ODTEN_CK(HSRX_ODTEN_CK),
.HSRX_ODTEN_D0(HSRX_ODTEN_D0),
.HSRX_ODTEN_D1(HSRX_ODTEN_D1),
.HSRX_ODTEN_D2(HSRX_ODTEN_D2),
.HSRX_ODTEN_D3(HSRX_ODTEN_D3),
.HSRX_STOP(HSRX_STOP),
.HS_8BIT_MODE(HS_8BIT_MODE),
.LALIGN_EN(LALIGN_EN),
.LPRX_EN_CK(LPRX_EN_CK),
.LPRX_EN_D0(LPRX_EN_D0),
.LPRX_EN_D1(LPRX_EN_D1),
.LPRX_EN_D2(LPRX_EN_D2),
.LPRX_EN_D3(LPRX_EN_D3),
.LPTX_EN_CK(LPTX_EN_CK),
.LPTX_EN_D0(LPTX_EN_D0),
.LPTX_EN_D1(LPTX_EN_D1),
.LPTX_EN_D2(LPTX_EN_D2),
.LPTX_EN_D3(LPTX_EN_D3),
.ONE_BYTE0_MATCH(ONE_BYTE0_MATCH),
.PWRON(PWRON),
.RESET(RESET),
.RX0_N(RX0_N),
.RX0_P(RX0_P),
.RX1_N(RX1_N),
.RX1_P(RX1_P),
.RX2_N(RX2_N),
.RX2_P(RX2_P),
.RX3_N(RX3_N),
.RX3_P(RX3_P),
.RX_CLK_1X(RX_CLK_1X),
.RX_CLK_O(RX_CLK_O),
.RX_INVERT(RX_INVERT),
.WALIGN_BY(WALIGN_BY),
.WALIGN_DVLD(WALIGN_DVLD),
.WORD_LENDIAN(WORD_LENDIAN)
);The MIPI_IBUF primitive supports two modes: LP (Low-Power) mode and HS (High-Speed) mode. In LP mode, it provides bi-directional functionality with different behavior based on the state of the OEN and OENB inputs. When OEN is low, I is input and IO is output; when OEN is high, IO is input and OL is output; when OENB is low, IB is input and IOB is output; when OENB is high, IOB is input and OB is output. In HS mode, IO and IOB are the differential inputs, with OH as the output, and HSREN controlling the termination resistor.
This device is not yet supported in Apicula
| Port | Size | Direction |
|---|---|---|
| HSEN | 1 | input |
| HSREN | 1 | input |
| I | 1 | input |
| IB | 1 | input |
| IO | 1 | inout |
| IOB | 1 | inout |
| OB | 1 | output |
| OEN | 1 | input |
| OENB | 1 | input |
| OH | 1 | output |
| OL | 1 | output |
MIPI_IBUF mipi_ibuf_inst (
.HSEN(HSEN),
.HSREN(HSREN),
.I(I),
.IB(IB),
.IO(IO),
.IOB(IOB),
.OB(OB),
.OEN(OEN),
.OENB(OENB),
.OH(OH),
.OL(OL)
);This device is not yet supported in Apicula
| Port | Size | Direction |
|---|---|---|
| I | 1 | input |
| IB | 1 | input |
| OH | 1 | output |
MIPI_IBUF_HS mipi_ibuf_hs_inst (
.I(I),
.IB(IB),
.OH(OH)
);This device is not yet supported in Apicula
| Port | Size | Direction |
|---|---|---|
| I | 1 | input |
| IB | 1 | input |
| OB | 1 | output |
| OL | 1 | output |
MIPI_IBUF_LP mipi_ibuf_lp_inst (
.I(I),
.IB(IB),
.OB(OB),
.OL(OL)
);The MIPI_OBUF primitive is used as an (HS) MIPI output buffer when the MODESEL input is high, and as a (LP) MIPI output buffer when the MODESEL input is low. It does not provide any additional information about its functionality beyond this mode-dependent behavior.
This device is not yet supported in Apicula
| Port | Size | Direction |
|---|---|---|
| I | 1 | input |
| IB | 1 | input |
| MODESEL | 1 | input |
| O | 1 | output |
| OB | 1 | output |
MIPI_OBUF mipi_obuf_inst (
.I(I),
.IB(IB),
.MODESEL(MODESEL),
.O(O),
.OB(OB)
);The MIPI_OBUF_A primitive is used as a (HS) MIPI output buffer when MODESEL is high, and as a (LP) MIPI output buffer with IL signal input in LP mode when MODESEL is low. It supports devices from the LittleBee GW1N and GW1NR series, apart from those listed in Table 3-12, as per Table 3-14, and does not support certain specific devices such as GW5A-138B, GW5AS-138B, GW5AST-138B, GW5AT-138B, and GW5AT-75B.
This device is not yet supported in Apicula
| Port | Size | Direction |
|---|---|---|
| I | 1 | input |
| IB | 1 | input |
| IL | 1 | input |
| IO | 1 | inout |
| IOB | 1 | inout |
| MODESEL | 1 | input |
| O | 1 | output |
| OB | 1 | output |
| OEN | 1 | input |
| OENB | 1 | input |
MIPI_OBUF_A mipi_obuf_a_inst (
.I(I),
.IB(IB),
.IL(IL),
.IO(IO),
.IOB(IOB),
.MODESEL(MODESEL),
.O(O),
.OB(OB),
.OEN(OEN),
.OENB(OENB)
);