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updating script to find reset name and include it in assertion
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Michael Norris committed Jan 29, 2024
1 parent 193cc39 commit 4fb774f
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Showing 12 changed files with 16 additions and 12 deletions.
2 changes: 1 addition & 1 deletion src/datavault/rtl/dv_reg.sv
Original file line number Diff line number Diff line change
Expand Up @@ -481,6 +481,6 @@ module dv_reg (
assign cpuif_rd_data = readback_data;
assign cpuif_rd_err = readback_err;

`CALIPTRA_ASSERT_KNOWN(ERR_HWIF_IN, hwif_in, clk, '1)
`CALIPTRA_ASSERT_KNOWN(ERR_HWIF_IN, hwif_in, clk, hwif_in.hard_reset_b)

endmodule
2 changes: 1 addition & 1 deletion src/doe/rtl/doe_reg.sv
Original file line number Diff line number Diff line change
Expand Up @@ -1409,6 +1409,6 @@ module doe_reg (
assign cpuif_rd_data = readback_data;
assign cpuif_rd_err = readback_err;

`CALIPTRA_ASSERT_KNOWN(ERR_HWIF_IN, hwif_in, clk, '1)
`CALIPTRA_ASSERT_KNOWN(ERR_HWIF_IN, hwif_in, clk, hwif_in.reset_b)

endmodule
2 changes: 1 addition & 1 deletion src/ecc/rtl/ecc_reg.sv
Original file line number Diff line number Diff line change
Expand Up @@ -1814,6 +1814,6 @@ module ecc_reg (
assign cpuif_rd_data = readback_data;
assign cpuif_rd_err = readback_err;

`CALIPTRA_ASSERT_KNOWN(ERR_HWIF_IN, hwif_in, clk, '1)
`CALIPTRA_ASSERT_KNOWN(ERR_HWIF_IN, hwif_in, clk, hwif_in.reset_b)

endmodule
2 changes: 1 addition & 1 deletion src/hmac/rtl/hmac_reg.sv
Original file line number Diff line number Diff line change
Expand Up @@ -2054,6 +2054,6 @@ module hmac_reg (
assign cpuif_rd_data = readback_data;
assign cpuif_rd_err = readback_err;

`CALIPTRA_ASSERT_KNOWN(ERR_HWIF_IN, hwif_in, clk, '1)
`CALIPTRA_ASSERT_KNOWN(ERR_HWIF_IN, hwif_in, clk, hwif_in.reset_b)

endmodule
2 changes: 1 addition & 1 deletion src/keyvault/rtl/kv_reg.sv
Original file line number Diff line number Diff line change
Expand Up @@ -443,6 +443,6 @@ module kv_reg (
assign cpuif_rd_data = readback_data;
assign cpuif_rd_err = readback_err;

`CALIPTRA_ASSERT_KNOWN(ERR_HWIF_IN, hwif_in, clk, '1)
`CALIPTRA_ASSERT_KNOWN(ERR_HWIF_IN, hwif_in, clk, hwif_in.reset_b)

endmodule
2 changes: 1 addition & 1 deletion src/pcrvault/rtl/pv_reg.sv
Original file line number Diff line number Diff line change
Expand Up @@ -294,6 +294,6 @@ module pv_reg (
assign cpuif_rd_data = readback_data;
assign cpuif_rd_err = readback_err;

`CALIPTRA_ASSERT_KNOWN(ERR_HWIF_IN, hwif_in, clk, '1)
`CALIPTRA_ASSERT_KNOWN(ERR_HWIF_IN, hwif_in, clk, hwif_in.hard_reset_b)

endmodule
2 changes: 1 addition & 1 deletion src/sha256/rtl/sha256_reg.sv
Original file line number Diff line number Diff line change
Expand Up @@ -1426,6 +1426,6 @@ module sha256_reg (
assign cpuif_rd_data = readback_data;
assign cpuif_rd_err = readback_err;

`CALIPTRA_ASSERT_KNOWN(ERR_HWIF_IN, hwif_in, clk, '1)
`CALIPTRA_ASSERT_KNOWN(ERR_HWIF_IN, hwif_in, clk, hwif_in.reset_b)

endmodule
2 changes: 1 addition & 1 deletion src/sha512/rtl/sha512_reg.sv
Original file line number Diff line number Diff line change
Expand Up @@ -2025,6 +2025,6 @@ module sha512_reg (
assign cpuif_rd_data = readback_data;
assign cpuif_rd_err = readback_err;

`CALIPTRA_ASSERT_KNOWN(ERR_HWIF_IN, hwif_in, clk, '1)
`CALIPTRA_ASSERT_KNOWN(ERR_HWIF_IN, hwif_in, clk, hwif_in.reset_b)

endmodule
2 changes: 1 addition & 1 deletion src/soc_ifc/rtl/mbox_csr.sv
Original file line number Diff line number Diff line change
Expand Up @@ -581,6 +581,6 @@ module mbox_csr (
assign cpuif_rd_data = readback_data;
assign cpuif_rd_err = readback_err;

`CALIPTRA_ASSERT_KNOWN(ERR_HWIF_IN, hwif_in, clk, '1)
`CALIPTRA_ASSERT_KNOWN(ERR_HWIF_IN, hwif_in, clk, hwif_in.cptra_rst_b)

endmodule
2 changes: 1 addition & 1 deletion src/soc_ifc/rtl/sha512_acc_csr.sv
Original file line number Diff line number Diff line change
Expand Up @@ -1616,6 +1616,6 @@ module sha512_acc_csr (
assign cpuif_rd_data = readback_data;
assign cpuif_rd_err = readback_err;

`CALIPTRA_ASSERT_KNOWN(ERR_HWIF_IN, hwif_in, clk, '1)
`CALIPTRA_ASSERT_KNOWN(ERR_HWIF_IN, hwif_in, clk, hwif_in.cptra_rst_b)

endmodule
2 changes: 1 addition & 1 deletion src/soc_ifc/rtl/soc_ifc_reg.sv
Original file line number Diff line number Diff line change
Expand Up @@ -5684,6 +5684,6 @@ module soc_ifc_reg (
assign cpuif_rd_data = readback_data;
assign cpuif_rd_err = readback_err;

`CALIPTRA_ASSERT_KNOWN(ERR_HWIF_IN, hwif_in, clk, '1)
`CALIPTRA_ASSERT_KNOWN(ERR_HWIF_IN, hwif_in, clk, hwif_in.cptra_rst_b)

endmodule
6 changes: 5 additions & 1 deletion tools/scripts/rdl_post_process.py
Original file line number Diff line number Diff line change
Expand Up @@ -36,6 +36,10 @@ def scrub_line_by_line(fname):
has_unpacked = re.search(r'\[\d+\]', line)
has_struct = re.search(r'\bstruct\b\s*(?:unpacked)?', line)
is_endmodule = re.search(r'\bendmodule\b', line)
has_reset = re.search(r'\bnegedge.+\_b\b', line)
if (has_reset is not None):
substring = re.search(r"negedge (\w+.\w+)", line)
reset_name = substring.group(1)
# Skip lines with logic assignments or references to signals; we
# only want to scrub signal definitions for unpacked arrays
if (has_assign is not None or has_reg_strb is not None):
Expand All @@ -58,7 +62,7 @@ def scrub_line_by_line(fname):
mod_cnt+=1
elif (is_endmodule is not None):
mod_lines+="\n"
mod_lines+="`CALIPTRA_ASSERT_KNOWN(ERR_HWIF_IN, hwif_in, clk, '1)\n"
mod_lines+="`CALIPTRA_ASSERT_KNOWN(ERR_HWIF_IN, hwif_in, clk, " + reset_name + ")\n"
mod_lines+="\n"
mod_lines+=line
else:
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