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[HW] Bump CVA6, fpnew, and ancillary dependencies #262
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Signed-off-by: Nils Wistoff <[email protected]>
Signed-off-by: Nils Wistoff <[email protected]>
Signed-off-by: Nils Wistoff <[email protected]>
Signed-off-by: Nils Wistoff <[email protected]>
Signed-off-by: Nils Wistoff <[email protected]>
This reverts commit 304e4f8.
Signed-off-by: Nils Wistoff <[email protected]>
CVA6 bump made some checks fail with the restrictive 300 cycles threshold
Signed-off-by: Nils Wistoff <[email protected]>
Signed-off-by: Nils Wistoff <[email protected]>
Signed-off-by: Nils Wistoff <[email protected]>
Signed-off-by: Nils Wistoff <[email protected]>
axi2apb_64_32 has been deprecated. Replace it by the up-to-date axi and apb IPs. Signed-off-by: Nils Wistoff <[email protected]>
Signed-off-by: Nils Wistoff <[email protected]>
Signed-off-by: Nils Wistoff <[email protected]>
Signed-off-by: Nils Wistoff <[email protected]>
Signed-off-by: Nils Wistoff <[email protected]>
Signed-off-by: Nils Wistoff <[email protected]>
Signed-off-by: Nils Wistoff <[email protected]>
Signed-off-by: Nils Wistoff <[email protected]>
Signed-off-by: Nils Wistoff <[email protected]>
Signed-off-by: Nils Wistoff <[email protected]>
Signed-off-by: Nils Wistoff <[email protected]>
Signed-off-by: Nils Wistoff <[email protected]>
Signed-off-by: Nils Wistoff <[email protected]>
Signed-off-by: Nils Wistoff <[email protected]>
Signed-off-by: Nils Wistoff <[email protected]>
Signed-off-by: Nils Wistoff <[email protected]>
Signed-off-by: Nils Wistoff <[email protected]>
Signed-off-by: Nils Wistoff <[email protected]>
Signed-off-by: Nils Wistoff <[email protected]>
Signed-off-by: Nils Wistoff <[email protected]>
Signed-off-by: Nils Wistoff <[email protected]>
Signed-off-by: Nils Wistoff <[email protected]>
Signed-off-by: Nils Wistoff <[email protected]>
Signed-off-by: Nils Wistoff <[email protected]>
Signed-off-by: Nils Wistoff <[email protected]>
Otherwise, warnings are actually blocking
The addrgen-sldu operand queue is common to slide unit and addrgen. Since it's shared, we should be sure not to sample a spurious ready from the wrong unit, i.e., when we are feeding the addrgen, we don't want spurious readies from the slide unit. The units should be responsible for avoiding sampling wrong data, but spurious ready signals can happen in specific corner cases. Fixing this without impacting timing is hard, so we just mask the ready signals here as well to avoid bugs.
Implement clock gating on the unused cache banks
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Update the system's dependencies and use Bender as default for hardware dependency management.
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