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[HW] Bump CVA6, fpnew, and ancillary dependencies #262

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Dec 1, 2023
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@mp-17 mp-17 commented Nov 13, 2023

Update the system's dependencies and use Bender as default for hardware dependency management.

Changelog

Fixed

  • Filter operand queue ready_i from addrgen and sldu selectively when they should not handshake
  • CI: don't check the patch directory for whitespace changes

Changed

  • Bump CVA6 version following OpenHW Group's modification
  • Bump fpnew to CVFPU
  • Switch from git submodules to Bender to handle hardware dependencies
  • Bump AXI, tech_cells_generic, and common_cells dependencies

Checklist

  • Automated tests pass
  • Implement cache bank clk gating in CVA6
  • Changelog updated
  • Code style guideline is observed

niwis and others added 28 commits November 29, 2023 13:29
Signed-off-by: Nils Wistoff <[email protected]>
Signed-off-by: Nils Wistoff <[email protected]>
CVA6 bump made some checks fail with the restrictive 300 cycles threshold
Signed-off-by: Nils Wistoff <[email protected]>
Signed-off-by: Nils Wistoff <[email protected]>
axi2apb_64_32 has been deprecated. Replace it by the up-to-date axi and
apb IPs.

Signed-off-by: Nils Wistoff <[email protected]>
Signed-off-by: Nils Wistoff <[email protected]>
Signed-off-by: Nils Wistoff <[email protected]>
Signed-off-by: Nils Wistoff <[email protected]>
Signed-off-by: Nils Wistoff <[email protected]>
Signed-off-by: Nils Wistoff <[email protected]>
Signed-off-by: Nils Wistoff <[email protected]>
niwis and others added 19 commits November 29, 2023 13:30
Signed-off-by: Nils Wistoff <[email protected]>
Signed-off-by: Nils Wistoff <[email protected]>
Otherwise, warnings are actually blocking
The addrgen-sldu operand queue is common to slide unit and addrgen.
Since it's shared, we should be sure not to sample a
spurious ready from the wrong unit, i.e., when we are
feeding the addrgen, we don't want spurious readies from
the slide unit. The units should be responsible for avoiding
sampling wrong data, but spurious ready signals can happen in
specific corner cases. Fixing this without impacting timing is
hard, so we just mask the ready signals here as well to avoid
bugs.
Implement clock gating on the unused cache banks
@mp-17 mp-17 marked this pull request as ready for review December 1, 2023 09:44
@mp-17 mp-17 merged commit c5c56ae into main Dec 1, 2023
197 checks passed
@mp-17 mp-17 deleted the mp/cva6-rebase branch December 1, 2023 17:06
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2 participants