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[HW] Bump CVA6, fpnew, and ancillary dependencies #262
Commits on Nov 29, 2023
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Signed-off-by: Nils Wistoff <[email protected]>
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ara_soc: Fix Ariane config param
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Makefile: Demote verilate warnings
Signed-off-by: Nils Wistoff <[email protected]>
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ara_system: Propatage AXI parameters to CVA6
Signed-off-by: Nils Wistoff <[email protected]>
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hw/Makefile: Update CVA6 target and defines
Signed-off-by: Nils Wistoff <[email protected]>
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[scripts] Increase HW-SW cycle check delta
CVA6 bump made some checks fail with the restrictive 300 cycles threshold
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Signed-off-by: Nils Wistoff <[email protected]>
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hw/Makefile: Update CVA6 target
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vmfpu: Remove unavailable fpnew ports
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axi2apb_64_32 has been deprecated. Replace it by the up-to-date axi and apb IPs. Signed-off-by: Nils Wistoff <[email protected]>
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Signed-off-by: Nils Wistoff <[email protected]>
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Bender.yml: Rename package ariane to cva6
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cva6: Bump (remove stall signls)
Signed-off-by: Nils Wistoff <[email protected]>
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cva6: Bump (move accel_disp and merge commit)
Signed-off-by: Nils Wistoff <[email protected]>
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scripts/wave_core.tcl: Update CVA6 module hierarchy
Signed-off-by: Nils Wistoff <[email protected]>
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cva6_accel_first_pass_decoder: Merge other accel decode logic
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cva6: Unify accelerator and CVX interface
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cva6: Bump (acc_port invalidation)
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ara_system: Pack inval interface into acc interface
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cva6: Bump (merge fu_data mux)
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cva6: Bump (cva6_accel_first_pass_decoder_stub)
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cva6: Bump (acc_req in acc_pkg)
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cva6: Bump (rem unused signals)
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cva6: Bump (cv32a6_embedded_config_pkg)
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[hardware] Disable -Wall in verilator
Otherwise, warnings are actually blocking
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[hardware] 🐛 Filter operand queue ready from sldu and addrgen
The addrgen-sldu operand queue is common to slide unit and addrgen. Since it's shared, we should be sure not to sample a spurious ready from the wrong unit, i.e., when we are feeding the addrgen, we don't want spurious readies from the slide unit. The units should be responsible for avoiding sampling wrong data, but spurious ready signals can happen in specific corner cases. Fixing this without impacting timing is hard, so we just mask the ready signals here as well to avoid bugs.
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[Bender] Bump CVA6 and fix its commit
Implement clock gating on the unused cache banks
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Commits on Dec 1, 2023
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