[HW] Bump CVA6, fpnew, and ancillary dependencies

.github/workflows/ci.yml

@@ -277,7 +277,7 @@ jobs:
         ln -s $VERILATOR_ROOT/share/verilator/include $VERILATOR_ROOT/include
         ln -s $VERILATOR_ROOT/share/verilator/bin/verilator_includer $VERILATOR_ROOT/bin/verilator_includer
     - name: Download RTL submodules
-      run: git submodule update --init --recursive hardware
+      run: make -C hardware update
     - name: Compile Verilated model of Ara
       run: |
         sudo apt-get install libelf-dev
@@ -454,9 +454,10 @@ jobs:
     # are mandatory there if they exist.
     - name: Check for trailing whitespaces and tabs
       run: |
-        git diff --check $base HEAD -- \
-        apps config hardware .github   \
-        *.md Bender.* Makefile
+        bash -O extglob -c                \
+        "git diff --check $base HEAD --   \
+        apps config .github *.md Bender.* \
+        Makefile hardware/!(patches)"
 
 #####################
 #  Benchmark stage  #

.gitmodules

@@ -9,21 +9,6 @@
 [submodule "toolchain/verilator"]
 	path = toolchain/verilator
 	url = https://github.com/verilator/verilator
-[submodule "hardware/deps/axi"]
-	path = hardware/deps/axi
-	url = https://github.com/pulp-platform/axi.git
-[submodule "hardware/deps/common_cells"]
-	path = hardware/deps/common_cells
-	url = https://github.com/pulp-platform/common_cells.git
-[submodule "hardware/deps/tech_cells_generic"]
-	path = hardware/deps/tech_cells_generic
-	url = https://github.com/pulp-platform/tech_cells_generic.git
-[submodule "hardware/deps/common_verification"]
-	path = hardware/deps/common_verification
-	url = https://github.com/pulp-platform/common_verification.git
-[submodule "hardware/deps/cva6"]
-	path = hardware/deps/cva6
-	url = https://github.com/pulp-platform/cva6.git
 [submodule "toolchain/newlib"]
 	path = toolchain/newlib
 	url = https://sourceware.org/git/newlib-cygwin.git
@@ -32,6 +17,3 @@
 	path = toolchain/riscv-llvm
 	url = https://github.com/llvm/llvm-project.git
 	ignore = dirty
-[submodule "hardware/deps/apb"]
-	path = hardware/deps/apb
-	url = https://github.com/pulp-platform/apb.git

Bender.local

@@ -0,0 +1,7 @@
+# Copyright 2023 ETH Zurich and University of Bologna.
+# Solderpad Hardware License, Version 0.51, see LICENSE for details.
+# SPDX-License-Identifier: SHL-0.51
+
+overrides:
+  axi:                { git: "https://github.com/pulp-platform/axi.git",                version: 0.39.1 }
+  tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.13 }

Bender.lock

@@ -1,4 +1,3 @@
----
 packages:
   apb:
     revision: 77ddf073f194d44b9119949d2421be59789e69ae
@@ -7,38 +6,58 @@ packages:
       Git: https://github.com/pulp-platform/apb.git
     dependencies:
     - common_cells
+  ariane:
+    revision: 2ebe023f7289300348c68e99267afcc03256f3ed
+    version: null
+    source:
+      Git: https://github.com/pulp-platform/cva6.git
+    dependencies:
+    - axi
+    - common_cells
+    - fpnew
+    - tech_cells_generic
   axi:
-    revision: 442ff3375710513623f95944d66cc2bd09b2f155
-    version: 0.29.1
+    revision: fccffb5953ec8564218ba05e20adbedec845e014
+    version: 0.39.1
     source:
-      Git: "https://github.com/pulp-platform/axi.git"
+      Git: https://github.com/pulp-platform/axi.git
     dependencies:
-      - common_cells
-      - common_verification
+    - common_cells
+    - common_verification
+    - tech_cells_generic
   common_cells:
-    revision: 015917ff33e5f944e866814f72f2074fb0f4220f
-    version: 1.22.1
+    revision: 2bd027cb87eaa9bf7d17196ec5f69864b35b630f
+    version: 1.32.0
     source:
-      Git: "https://github.com/pulp-platform/common_cells.git"
+      Git: https://github.com/pulp-platform/common_cells.git
     dependencies:
-      - common_verification
-      - tech_cells_generic
+    - common_verification
+    - tech_cells_generic
   common_verification:
-    revision: 6fc76fb013315af9fabbb90b431863d498df2d6d
-    version: 0.2.0
+    revision: 9c07fa860593b2caabd9b5681740c25fac04b878
+    version: 0.2.3
     source:
-      Git: "https://github.com/pulp-platform/common_verification.git"
+      Git: https://github.com/pulp-platform/common_verification.git
     dependencies: []
-  cva6:
-    revision: 3245e44ec49c1cdcd19eb298cd81f0672eaf81ca
-    version: ~
+  fpnew:
+    revision: 3116391bf66660f806b45e212b9949c528b4e270
+    version: 0.7.0
     source:
-      Git: "https://github.com/pulp-platform/cva6.git"
-    dependencies: []
+      Git: https://github.com/openhwgroup/cvfpu.git
+    dependencies:
+    - common_cells
+    - fpu_div_sqrt_mvp
+  fpu_div_sqrt_mvp:
+    revision: 86e1f558b3c95e91577c41b2fc452c86b04e85ac
+    version: 1.0.4
+    source:
+      Git: https://github.com/pulp-platform/fpu_div_sqrt_mvp.git
+    dependencies:
+    - common_cells
   tech_cells_generic:
-    revision: 203038f857158ae4634c47ce0281f402cc2a1344
-    version: 0.2.4
+    revision: 7968dd6e6180df2c644636bc6d2908a49f2190cf
+    version: 0.2.13
     source:
-      Git: "https://github.com/pulp-platform/tech_cells_generic.git"
+      Git: https://github.com/pulp-platform/tech_cells_generic.git
     dependencies:
-      - common_verification
+    - common_verification

Bender.yml

@@ -8,11 +8,11 @@ package:
     - "Paul Scheffler <[email protected]>"
 
 dependencies:
-  axi:                { git: "https://github.com/pulp-platform/axi.git",                version: 0.29.1 }
-  common_cells:       { git: "https://github.com/pulp-platform/common_cells.git",       version: 1.22.1 }
-  cva6:               { git: "https://github.com/pulp-platform/cva6.git",               rev: acc_port   }
-  tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.1  }
-  apb:                { git: "https://github.com/pulp-platform/apb.git",                version: 0.2.4  }
+  axi:                { git: "https://github.com/pulp-platform/axi.git",                version: 0.39.1                               }
+  common_cells:       { git: "https://github.com/pulp-platform/common_cells.git",       version: 1.22.1                               }
+  ariane:             { git: "https://github.com/pulp-platform/cva6.git",               rev: 2ebe023f7289300348c68e99267afcc03256f3ed } # mp/acc_port_rebase
+  tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.13                               }
+  apb:                { git: "https://github.com/pulp-platform/apb.git",                version: 0.2.4                                }
 
 workspace:
   checkout_dir: "hardware/deps"

CHANGELOG.md

@@ -80,6 +80,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
  - Reset gating registers before the integer multipliers in `vmfpu`
  - Fix narrowing for `vnclip` and `vnclipu`
  - NaN-box the scalar value before forwarding back to CVA6
+ - Filter operand queue ready_i from addrgen and sldu selectively when they should not handshake
+ - CI: don't check the patch directory for whitespace changes
 
 ### Added
 
@@ -189,6 +191,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
  - Simplify the datapath of the slide unit. The `sldu` supports only powers of two, and cannot slide and reshuffle at the same time. Non-power-of-two slides are now handled with micro operations.
  - Bump Verilator to v5.012
  - Only allow one workflow at a time per branch/PR
+ - Bump CVA6 version following OpenHW Group's modification
+ - Bump fpnew to CVFPU
+ - Switch from git submodules to Bender to handle hardware dependencies
+ - Bump AXI, tech_cells_generic, and common_cells dependencies
 
 ## 2.2.0 - 2021-11-02
 

README.md

@@ -97,13 +97,38 @@ make riscv_tests
 
 ## RTL Simulation
 
-To simulate the Ara system with ModelSim, go to the `hardware` folder, which contains all the SystemVerilog files. Use the following command to run your simulation:
+### Hardware dependencies
+
+The Ara repository depends on external IPs and uses Bender to handle the IP dependencies.
+To install Bender and initialize all the hardware IPs, run the following commands:
+
+```bash
+# Go to the hardware folder
+cd hardware
+# Install Bender and checkout all the IPs
+make update
+```
+
+### Patches (only once!)
+
+Note: this step is required only once, and needs to be repeated ONLY if the IP hardware dependencies are deleted and checked out again.
+
+Some of the IPs need to be patched to work with Verilator.
 
 ```bash
 # Go to the hardware folder
 cd hardware
 # Apply the patches (only need to run this once)
 make apply-patches
+```
+
+### Simulation
+
+To simulate the Ara system with ModelSim, go to the `hardware` folder, which contains all the SystemVerilog files. Use the following command to run your simulation:
+
+```bash
+# Go to the hardware folder
+cd hardware
 # Only compile the hardware without running the simulation.
 make compile
 # Run the simulation with the *hello_world* binary loaded

hardware/Makefile

@@ -10,6 +10,9 @@ ARA_DIR := $(shell git rev-parse --show-toplevel 2>/dev/null || echo $$ARA_DIR)
 INSTALL_DIR := $(abspath $(ROOT_DIR)/../install)
 VERILATOR_INCLUDE := $(INSTALL_DIR)/verilator/share/verilator/include/vltstd
 
+BENDER         := $(ROOT_DIR)/../hardware/bender
+BENDER_VERSION := 0.27.3
+
 # Choose Ara's configuration
 ifndef config
 	ifdef ARA_CONFIGURATION
@@ -101,8 +104,14 @@ dpi   := $(patsubst tb/dpi/%.cc,$(buildpath)/$(dpi_library)/%.o,$(wildcard tb/dp
 vlog_args += -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233
 vlog_args += -work $(library)
 
+# Bender
 # Defines
-bender_defs += --define NR_LANES=$(nr_lanes) --define VLEN=$(vlen) --define RVV_ARIANE=1
+bender_defs += --define NR_LANES=$(nr_lanes) --define VLEN=$(vlen) --define ARIANE_ACCELERATOR_PORT=1
+# Targets
+bender_common_targs := -t rtl -t cv64a6_imafdcv_sv39 -t tech_cells_generic_include_tc_sram -t tech_cells_generic_include_tc_clk
+bender_targs_simc     := $(bender_common_targs) -t ara_test -t cva6_test
+bender_targs_veril    := $(bender_common_targs) -t ara_test -t cva6_test -t verilator
+bender_targs_spyglass := $(bender_common_targs) -t spyglass
 
 # Default target
 all: compile
@@ -111,12 +120,22 @@ all: compile
 $(buildpath):
 	mkdir -p $(buildpath)
 
+.PHONY: bender update
 # Bender
-bender:
-	@[ -x ./bender ] && echo "Bender already exists." || \
-	curl --proto '=https' --tlsv1.2 https://fabianschuiki.github.io/bender/init -sSf | sh	-s -- 0.23.1
+bender: $(BENDER)
+$(BENDER):
+	@[ -x $(BENDER) ] && echo "Bender already exists." || \
+	curl --proto '=https' --tlsv1.2 https://pulp-platform.github.io/bender/init -sSf | sh	-s -- $(BENDER_VERSION)
 	@echo "$$(./bender --version) available."
 
+update: $(BENDER) $(ROOT_DIR)/../Bender.yml
+	rm -rf $(ROOT_DIR)/../hardware/deps/*
+	$(BENDER) update -f
+	$(BENDER) checkout
+
+checkout: $(BENDER)
+	$(BENDER) checkout
+
 # Patches
 .PHONY: apply-patches
 apply-patches: patches
@@ -132,11 +151,11 @@ $(buildpath)/$(library):
 .PHONY: compile
 compile: dpi lib $(buildpath) bender $(buildpath)/compile_$(config).tcl
 $(buildpath)/compile_$(config).tcl: $(config_file) Makefile ../Bender.yml $(shell find src -type f) $(shell find ../config -type f) $(shell find include -type f) $(shell find tb -type f) $(shell find deps -type f)
-	./bender script vsim --vlog-arg="$(vlog_args)" -t rtl -t asic -t ara_test -t cva6_test $(bender_defs) > $(buildpath)/compile_$(config).tcl
+	$(BENDER) script vsim --vlog-arg="$(vlog_args)" $(bender_targs_simc) $(bender_defs) > $(buildpath)/compile_$(config).tcl
 	echo "exit" >> $(buildpath)/compile_$(config).tcl
 	cd $(buildpath) && $(questa_cmd) vsim -work $(library) -c -do compile_$(config).tcl
-	# Remove the file if compilation did not succeed
-	if [ `cat $(buildpath)/transcript | grep "\*\* Error" | wc -l` -ne 0 ]; then rm $(buildpath)/compile_$(config).tcl; fi
+	# Rename the file if compilation did not succeed
+	if [ `cat $(buildpath)/transcript | grep "\*\* Error" | wc -l` -ne 0 ]; then mv $(buildpath)/compile_$(config).tcl $(buildpath)/compile_$(config).tcl.ERROR; fi
 
 # Simulation
 .PHONY: sim
@@ -164,11 +183,13 @@ verilate: $(buildpath) bender $(veril_library)/V$(veril_top)
 
 $(veril_library)/V$(veril_top): $(config_file) Makefile ../Bender.yml $(shell find src -type f) $(shell find ../config -type f) $(shell find include -type f) $(shell find tb -type f) $(shell find deps -type f)
 	rm -rf $(veril_library); mkdir -p $(veril_library)
-	./bender script verilator -t rtl -t ara_test -t cva6_test -t verilator $(bender_defs) > $(veril_library)/bender_script_$(config)
+	$(BENDER) script verilator $(bender_targs_veril) $(bender_defs) > $(veril_library)/bender_script_$(config)
 # Verilate the design
 	$(veril_path)/verilator -f $(veril_library)/bender_script_$(config)           \
   -GNrLanes=$(nr_lanes)                                                         \
   -O3                                                                           \
+  -Wno-fatal                                                                    \
+  -Wno-PINCONNECTEMPTY                                                          \
   -Wno-BLKANDNBLK                                                               \
   -Wno-CASEINCOMPLETE                                                           \
   -Wno-CMPCONST                                                                 \
@@ -180,7 +201,7 @@ $(veril_library)/V$(veril_top): $(config_file) Makefile ../Bender.yml $(shell fi
   -Wno-WIDTH                                                                    \
   -Wno-WIDTHCONCAT                                                              \
   -Wno-ENUMVALUE                                                                \
-  -Wno-COMBDLY \
+  -Wno-COMBDLY                                                                  \
   --hierarchical                                                                \
   tb/verilator/waiver.vlt                                                       \
   --Mdir $(veril_library)                                                       \
@@ -224,7 +245,7 @@ lint: spyglass/tmp/files spyglass/sdc/func.sdc spyglass/scripts/run_lint.tcl
 
 spyglass/tmp/files: $(bender)
 	mkdir -p spyglass/tmp
-	./bender script verilator -t rtl -t spyglass -t cva6_test $(bender_defs) --define SPYGLASS > spyglass/tmp/files
+	$(BENDER) script verilator $(bender_targs_spyglass) $(bender_defs) --define SPYGLASS > spyglass/tmp/files
 
 # DPIs
 .PHONY: dpi
@@ -242,4 +263,4 @@ $(buildpath)/$(dpi_library)/ara_dpi.so: $(dpi)
 .PHONY: clean
 clean:
 	rm -rf $(buildpath)
-	rm -f bender
+	rm -f  $(BENDER)

hardware/include/ara_pkg.sv

@@ -239,8 +239,8 @@ package ara_pkg;
   /////////////////////////////
 
   // Use Ariane's accelerator interface.
-  typedef ariane_pkg::accelerator_req_t accelerator_req_t;
-  typedef ariane_pkg::accelerator_resp_t accelerator_resp_t;
+  typedef acc_pkg::accelerator_req_t accelerator_req_t;
+  typedef acc_pkg::accelerator_resp_t accelerator_resp_t;
 
   /////////////////////////
   //  Backend interface  //