Merge pull request #1820 from YenHaoChen/pr-halt

refactor: Remove dcsr::halt variable
riscv-software-src · Sep 27, 2024 · 00cf1eb · 00cf1eb
2 parents 666da33 + 5c814c7
commit 00cf1eb
Show file tree

Hide file tree

Showing 4 changed files with 2 additions and 6 deletions.
diff --git a/riscv/csrs.cc b/riscv/csrs.cc
@@ -1345,7 +1345,6 @@ dcsr_csr_t::dcsr_csr_t(processor_t* const proc, const reg_t addr):
   ebreaku(false),
   ebreakvs(false),
   ebreakvu(false),
-  halt(false),
   v(false),
   cause(0),
   ext_cause(0),

diff --git a/riscv/csrs.h b/riscv/csrs.h
@@ -696,7 +696,6 @@ class dcsr_csr_t: public csr_t {
   bool ebreaku;
   bool ebreakvs;
   bool ebreakvu;
-  bool halt;
   bool v;
   uint8_t cause;
   uint8_t ext_cause;

diff --git a/riscv/execute.cc b/riscv/execute.cc
@@ -216,8 +216,8 @@ void processor_t::step(size_t n)
       enter_debug_mode(DCSR_CAUSE_DEBUGINT, 0);
     } else if (halt_request == HR_GROUP) {
       enter_debug_mode(DCSR_CAUSE_GROUP, 0);
-    } else if (state.dcsr->halt) {
-      state.dcsr->halt = false;
+    } else if (halt_on_reset) {
+      halt_on_reset = false;
       enter_debug_mode(DCSR_CAUSE_HALT, 0);
     }
   }

diff --git a/riscv/processor.cc b/riscv/processor.cc
@@ -186,8 +186,6 @@ void processor_t::reset()
 {
   xlen = isa.get_max_xlen();
   state.reset(this, isa.get_max_isa());
-  state.dcsr->halt = halt_on_reset;
-  halt_on_reset = false;
   if (any_vector_extensions())
     VU.reset();
   in_wfi = false;