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refactor: Remove dcsr::halt variable #1820

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merged 2 commits into from
Sep 27, 2024
Merged

refactor: Remove dcsr::halt variable #1820

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871d945
refactor: Move halt out of dcsr
YenHaoChen Sep 27, 2024
5c814c7
refactor: Merge halt and halt_on_reset variables in processor_t
YenHaoChen Sep 27, 2024
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1 change: 0 additions & 1 deletion riscv/csrs.cc
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Expand Up @@ -1345,7 +1345,6 @@ dcsr_csr_t::dcsr_csr_t(processor_t* const proc, const reg_t addr):
ebreaku(false),
ebreakvs(false),
ebreakvu(false),
halt(false),
v(false),
cause(0),
ext_cause(0),
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1 change: 0 additions & 1 deletion riscv/csrs.h
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Expand Up @@ -696,7 +696,6 @@ class dcsr_csr_t: public csr_t {
bool ebreaku;
bool ebreakvs;
bool ebreakvu;
bool halt;
bool v;
uint8_t cause;
uint8_t ext_cause;
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4 changes: 2 additions & 2 deletions riscv/execute.cc
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Expand Up @@ -216,8 +216,8 @@ void processor_t::step(size_t n)
enter_debug_mode(DCSR_CAUSE_DEBUGINT, 0);
} else if (halt_request == HR_GROUP) {
enter_debug_mode(DCSR_CAUSE_GROUP, 0);
} else if (state.dcsr->halt) {
state.dcsr->halt = false;
} else if (halt_on_reset) {
halt_on_reset = false;
enter_debug_mode(DCSR_CAUSE_HALT, 0);
}
}
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2 changes: 0 additions & 2 deletions riscv/processor.cc
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Expand Up @@ -186,8 +186,6 @@ void processor_t::reset()
{
xlen = isa.get_max_xlen();
state.reset(this, isa.get_max_isa());
state.dcsr->halt = halt_on_reset;
halt_on_reset = false;
if (any_vector_extensions())
VU.reset();
in_wfi = false;
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