Cutting back Xilinx ISE

Xilinx ISE tools are like 14 gigabytes, this is kind of sucky as not everyone has the space / bandwidth to use that. This includes some random notes about trying to cut back the Xilinx tools while still compiling the firmware;

Artiq has gotten some of this working on Travis with misoc/migen; see the following to bits;

• https://github.com/m-labs/artiq/blob/master/.travis.yml
• https://github.com/m-labs/migen/blob/master/tools/strace_tailor.sh

Joel Stanley also look at it; notes can be found at

• https://github.com/shenki/bindfs
• http://logs.timvideos.us/%23timvideos/%23timvideos.2014-06-03.log.html#t2014-06-03T14:47:55
• https://jms.id.au/~joel/xilinx-ec2-howto.txt