MIO

FPGA Firmware

A Xilinx project file (.xise) is available here.

Pin Assignments

• RJ45 Jack / TLU Port
  Connect the EUDET TLU here.

• LEMO Connectors
  Note: all inputs and outputs are using 3.3V CMOS logic levels
  RX0: External Trigger Input (also TDC FSM Trigger Input)
  RX1: Trigger or Veto Input
  RX2: TDC Input
  TX0: TLU Clock
  TX1: Trigger Busy when Trigger FSM enabled else CMD FSM busy
  TX2: Loop-through TLU Trigger (from TLU Port)

• Pin Header P9
  *1 – 10: not connected
  *11: Loop-through TDC Input (from RX2)
  *13, 15: GND
  *14, 16: VCC

Status LEDs

• LED 5 (System and SRAM FIFO status):
  • flashing at 1Hz: OK
  • off: DCM not locked
  • on: SRAM FIFO full

• LED 1-4 (RX FIFO status):
  • flashing at 1Hz: OK
  • flashing at 3Hz: RX 8b10b decoder error counter >0
  • off: no RX sync
  • on: RX FIFO overflow || RX FIFO full