MIO3

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Jens Janssen edited this page May 28, 2015 · 2 revisions

FPGA Firmware

A Xilinx project file (.xise) is available here.

Pin Assignments

RJ45 Jack / TLU Port
Connect the EUDET TLU here.

LEMO Connectors
Note: all inputs and outputs are using 3.3V CMOS logic levels
TBD

Status LEDs

TBD