Simulation

Preparing for Simulation

To run the simulation together with FE-I4A the following prerequisites needs to be installed:

pyBAR and basil

Please clone the pyBAR and basil git repository and place it into the same directory (e.g. “dev” folder).

FE-I4A Sources

If you want to run simulation with another firmware than the default one, FE-I4A Source are necessary. The FE-I4A sources are available to ATLAS members and can be downloaded here. Check out the SVN repository and place it into the same folder where pyBAR and basil are placed.

If no change to the firmware is necessary, the pre-compiled code in the .vvp file (inside sim_build.zip) can be used to run the simulation.

cocotb

Clone cocotb. Export cocotb path:

export COCOTB=/path/to/cocotb

Icarus Verilog

Install Icarus Verilog via package manager (Ubuntu strongly recommended):

sudo add-apt-repository -y ppa:team-electronics/ppa
sudo apt-get update
sudo apt-get install iverilog-daily

GTKWave

Install GTKWave via package manager:

sudo apt-get install gtkwave

XILINX Unisims

Export path to folder containing unisims folder (Xilinx Simulation Library):

export XILINX=/path/to/folder/containing/unisims/folder

Generating sim.vvp from Latest Firmware

Cd into firmware/mio/cosim and run:

make -f Makefile results.xml

The process does not need to finish, but the sim.vvp is created correctly. The execution can be aborted if no further progress is being made:

killall vvp

Zip the sim_build directory and and move the sim_build.zip into pybar/testing/test_interface_data/:

zip -r sim_build.zip sim_build
cp sim_build.zip ../../../pybar/testing/test_interface_data/

Running the Simulation

Starting the Simulation

Cd into pybar/testing and run:

python test_interface.py

Waveforms

Opening waveform with:

gtkwave tb.vcd

Q&A

1. Q: The following error occurs:
   vvp: symbol lookup error: /home/jens/miniconda/lib/libreadline.so.6: undefined symbol: PC
    
   A: Uninstall readline package:
   

   conda uninstall readline

   or remove library:
   

   rm -f /path/to/miniconda2/lib/libreadline.so.6

2. Q: The the .vcd file is not generated by vvp.
    
   A: The installed version of Icarus Verilog does not support fst file format. Remove the -fst argument that is passed to vvp in the Makefile.

3. Q: Simulation stopped with socket error.
    
   A: Kill all vvp processes.